This chapter describes customizing and generating the IP core, constraining the core, and the simulation, synthesis, and implementation steps specific to this core. More detailed information about the standard AMD Vivado ™ design flows and the Vivado IP integrator can be found in the following Vivado Design Suite user guides:
• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 7]
• Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 8]
• Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 9]
• Vivado Design Suite User Guide: Getting Started (UG910) [Ref 10]