Customizing and Generating the Core - 4.0 English - PG029

Quad Serial Gigabit Media Independent LogiCORE IP Product Guide (PG029)
Document ID
PG029
Release Date
2025-12-09
Version
4.0 English

This section includes information about using AMD Vitis™ tools to customize and generate the core in the AMD Vivado™ Design Suite.

If you are customizing and generating the core in the IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl console.

You can customize the IP for use in your design by specifying values for the parameters associated with the IP core:

  1. Select the IP from the AMD Vivado™ IP catalog.
  2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).

Figures in this chapter are illustrations of the Vivado IDE. This layout might vary from the current version.

All parameters are available and modifiable in the IP integrator. The default configuration of the core in the IP integrator is the same as the that generated though the IP catalog.

Core Customization Vivado IDE

The following screenshot displays the QSGMII customization Vivado IDE, used to set core parameters and options. For help starting and using Vivado design tools on your system, see the documentation included with the Vivado Design Suite.

Core Customization Screen

Figure 1. Core Customization Screen (Non-Versal Devices)
Figure 2. Core Customization Screen (Versal Devices)
Component Name
The component name is the base name of the output files generated for the core. Names must begin with a letter and can include alphanumeric characters and the underscore (_).
Use Legacy GT Wizard in Example design
This option is available only for Versal Devices:
  • 1 - Versal Adaptive SoC Transceivers Wizard
  • 0 - Versal Adaptive SoC Transceivers Wizard Subsystem
Select Mode
  • MAC Mode: QSGMII interfaces with the IP catalog Tri-mode Ethernet IP on the GMII client side.
  • PHY Mode: QSGMII can interface with third-party Ethernet IP cores. The client interface can be selected as GMII or MII.
MDIO Management Interface
Select this option to include the MDIO Management Interface to access the PCS Configuration registers. MDIO Management Interface is selected by default.
MDIO Configuration Interface
Select this option to include an additional configuration interface to program configuration register 0 and can be used in addition to the MDIO Management Interface. This option is always selected if MDIO Management Interface is disabled.
Auto-Negotiation
Select this option to include auto-negotiation functionality with the core. Auto-Negotiation is selected by default.
AN Configuration Interface
Select this option to include and additional configuration interface to program the AN Advertisement register (register 4). This option is valid only if Auto-Negotiation is enabled.
PHY Address Chx
Use this option to define the PHY address of the MDIO interface of individual channels in the core. The value should be in the range of 0 to 31.
RX Gmii Clk Source
This option selects the clock source of the receive path and gmii_rx interface. When the RXOUTCLK is selected, the entire receive datapath works on rxusrclk2 and the elastic buffer on the receive path is bypassed.
DRP Clock Frequency
This option is available only for UltraScale and UltraScale+ devices and if Additional Transceiver Control and Status Ports is selected. This indicates the DRP frequency operation, selectable between 6.25 MHz to 125 MHz.
Transceiver Clocking and Location
This option is only available when an UltraScale or UltraScale+ device is selected. This gives a list of possible sources for reference clock and location of channel for selection.
Additional Transceiver Control and Status Ports
If selected, enables additional transceiver control ports for DRP, TX Driver, RX Equalization, and other features such as PRBS.

Select Interface Vivado IDE

The following figure displays the QSGMII interface selection AMD Vivado™ IDE. This AMD Vivado™ IDE is only displayed if PHY Mode is selected in the Select Mode section in the initial customization screen.

Figure 3. Select Interface Vivado IDE

Shared Logic Options in Vivado IDE

The following figure displays the shared logic options and transceiver control and status selection in the Vivado IDE. However, Shared Logic tab is not available for Versal Adaptive SoC families.

Figure 4. Shared Logic Options

The Shared Logic determines whether some shared clocking logic is included as part ofthecore or as part of the example design.

User Parameters

The following table shows the relationship between the fields in the Vivado IDE and the User Parameters (which can be viewed in the Tcl console).

Vivado IDE Parameter to User Parameter Relationship

Vivado IDE Parameter/Value 1 User Parameter/Value 1 Default Value
Use Legacy GT Wizard in Example design 0,1 0
Mode Mode MAC_MODE
MAC MODE MAC_MODE
PHY MODE PHY_MODE
Management Options: MDIO Management Interface Management_Interface TRUE
Management Options: Management Configuration Interface Config_Interface FALSE
Management Options: Auto Negotiation Auto_Negotiation TRUE
Management Options: AN Configuration Interface AN_Config_Interface FALSE
PHY Address Ch0 C_PHYADDR_0 1
PHY Address Ch1 C_PHYADDR_1 2
PHY Address Ch2 C_PHYADDR_2 3
PHY Address Ch3 C_PHYADDR_3 4
RX Gmii Clk Source RxGmiiClkSrc TXOUTCLK
Additional transceiver control and status ports TransceiverControl FALSE
DRP Clock Frequency c_drpclkrate 75
Transceiver Clocking and Location: Transceiver Refclk RefClk refclk0
Transceiver Clocking and Location: Transceiver Locations Locations X0Y0
Select Interface GMII_or_MII_Mode GMII
GMII GMII
MII MII
Shared Logic SupportLevel Include_Shared_Logic_in_Example_Design
Include Shared Logic in Core Include_Shared_Logic_in_Core
Include Shared Logic in Example Design Include_Shared_Logic_in_Example_Design
  1. Parameter values are listed in the table where the Vivado IDE parameter value differs from the user parameter value. Such values are shown in this table as indented below the associated parameter.
  2. Use Legacy GT Wizard in Example design parameter is available only for Versal Devices.

Output Generation

The QSGMII solution delivers files into several filegroups. By default the filegroups necessary for use of the QSGMII or opening the IP example design are generated when the core is generated. If additional filegroups are required these can be selected using the generate option.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896).

The filegroups generated can be seen in the IP Sources tab of the Sources window where they are listed for each IP in the project. The filegroups available for the QSGMII solution are:

Examples

Includes all source required to be able to open and implement the IP example design project, that is, example design HDL and the example design XDC file.

Examples Simulation

Includes all source required to be able to simulate the IP example design project. This is the same list of HDL as the Examples filegroup with the addition of the demonstration test bench HDL.

Synthesis

Includes all synthesis sources required by the core. For the QSGMII solution this is a mix of both encrypted and unencrypted source. Only the unencrypted sources are visible.

Simulation

Includes all simulation sources required by the core. Simulation of the QSGMII solution at the core level is not supported without the addition of a test bench (not supplied). Simulation of the example design is supported.

Instantiation Template

Example instantiation template.

Miscellaneous

This provides simulations scripts and support files required for running netlist based functional simulation. The files delivered as part of this filegroup are not used or understood by Vivado design tools and as such this filegroup is not displayed. These files are delivered into the project source directory.