The constraints defined in this section are used when the core is operated in PHY_MODE.
Clock Period Constraints
The core has four instances of SGMII
cores. These constraints are valid only when the core is generated with the MODE
parameter set to PHY_MODE and the Interface parameter set to GMII in
the Vivado IDE. When implementing an external GMII,
the Transmitter Elastic Buffer embedded in the QSGMII block is used. The input
transmitter GMII signals are then synchronous to their own clock domain (gtx_clk_chx is used in the example design). These
clocks must be constrained for a clock frequency of 125 MHz. The following XDC
syntax shows the necessary constraints being applied to the example design.
#***********************************************************
# GMII GTX transceiver CLK for clocking in GMII TX Interface*
#***********************************************************
create_clock -add -name gtx_clk_ch0 -period 8.000 [get_ports gtx_clk_ch0]
create_clock -add -name gtx_clk_ch1 -period 8.000 [get_ports gtx_clk_ch1]
create_clock -add -name gtx_clk_ch2 -period 8.000 [get_ports gtx_clk_ch2]
create_clock -add -name gtx_clk_ch3 -period 8.000 [get_ports gtx_clk_ch3]GMII/MII IOB Constraints
The following constraints target the flip-flops that are inferred in the top-level HDL file for the example design. These constraints are defined for receive signals; the transmit GMII/MII interface passes through IDELAY modules to adjust for latency. See the following section for details. Constraints are set to ensure that these are placed in IOBs.
#***********************************************************
# GMII Receiver Constraints: place flip-flops in IOB *
#***********************************************************
set_property IOB TRUE [get_cells gmii_rxd_ch0_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rx_dv_ch0_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rx_er_ch0_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rxd_ch1_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rx_dv_ch1_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rx_er_ch1_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rxd_ch2_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rx_dv_ch2_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rx_er_ch2_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rxd_ch3_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rx_dv_ch3_obuf_reg*]
set_property IOB TRUE [get_cells gmii_rx_er_ch3_obuf_reg*]
#***********************************************************
# GMII IOSTANDARD Constraints: please select an I/O *
# Standard (LVTTL is suggested). *
#***********************************************************
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd_ch0[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en_ch0]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er_ch0]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd_ch0[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv_ch0]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er_ch0]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd_ch1[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd_ch1[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd_ch2[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd_ch2[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd_ch0[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv_ch0]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er_ch0]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd_ch1[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd_ch1[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd_ch2[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd_ch2[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_txd_ch3[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_en_ch3]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_tx_er_ch3]
set_property IOSTANDARD LVCMOS33 [get_ports {gmii_rxd_ch3[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_dv_ch3]
set_property IOSTANDARD LVCMOS33 [get_ports gmii_rx_er_ch3]
set_property IOSTANDARD LVCMOS33 [get_ports gtx_clk_ch0]
set_property IOSTANDARD LVCMOS33 [get_ports gtx_clk_ch1]
set_property IOSTANDARD LVCMOS33 [get_ports gtx_clk_ch2]
set_property IOSTANDARD LVCMOS33 [get_ports gtx_clk_ch3]GMII Input Setup/Hold Timing
The following tables illustrate the setup and hold time window for the input GMII signals. These are the worst-case data valid window presented to the FPGA pins.
Observe that there is, in total, a 2 ns data valid window of guaranteed data that is presented across the GMII input bus. This must be correctly sampled by the FPGA devices.
Input GMII Timings
| Symbol | Min | Max | Units |
|---|---|---|---|
| tSETUP | 2.00 | - | ns |
| tHOLD | 0.00 | - | ns |
Zynq 7000 SoC, Virtex 7, Kintex 7, and Artix 7 Devices
External GMII Transmitter Logic illustrates the GMII input logic provided in the core for the Zynq 7000 SoC, Virtex 7, Kintex 7, and Artix 7 family.
External MII Transmitter Logic illustrates the MII input logic provided in the core for the Zynq 7000 SoC, Virtex 7, Kintex 7, and Artix 7 family.
IODELAY elements are instantiated on the GMII/MII data input path as illustrated. Fixed tap delays are applied to these IODELAY elements to delay the GMII/MII input data signals so that data is correctly sampled at the IOB IDDR registers, thereby meeting GMII/MII input setup and hold timing constraints.
The number of tap delays are applied using the following XDC syntax.
#***********************************************************
# To Adjust GMII Tx Input Setup/Hold Timing *
#***********************************************************
# These constraints will be set at a later date when device speed files have matured
set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_en_ch0]
set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_er_ch0]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch0[7].delay_gmii_txd_ch0}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch0[6].delay_gmii_txd_ch0}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch0[5].delay_gmii_txd_ch0}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch0[4].delay_gmii_txd_ch0}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch0[3].delay_gmii_txd_ch0}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch0[2].delay_gmii_txd_ch0}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch0[1].delay_gmii_txd_ch0}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch0[0].delay_gmii_txd_ch0}]
set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_en_ch1]
set_property IDELAY_VALUE 0 [get_cells delay_gmii_tx_er_ch1]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch1[7].delay_gmii_txd_ch1}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch1[6].delay_gmii_txd_ch1}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch1[5].delay_gmii_txd_ch1}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch1[4].delay_gmii_txd_ch1}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch1[3].delay_gmii_txd_ch1}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch1[2].delay_gmii_txd_ch1}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch1[1].delay_gmii_txd_ch1}]
set_property IDELAY_VALUE 0 [get_cells {gmii_data_bus_ch1[0].delay_gmii_txd_ch1}]