Constraining the Core - 4.0 English - PG029

Quad Serial Gigabit Media Independent LogiCORE IP Product Guide (PG029)

Document ID
PG029
Release Date
2025-12-09
Version
4.0 English

This section contains information about constraining the core in the AMD Vivado™ Design Suite and defines the constraint requirements of the QSGMII core. An example XDC file is also provided with the HDL example design to provide the board level constraints. This is specific to the example design and, as such, is only expected to be used as a template for the user design. See Example Design. The XDC file, named <component name>_example_design.xdc, is found in the IP Sources tab of the Sources window in the Examples file group.