Virtex 7 Devices
The following figure illustrates sharing clock resources across two instantiations of the core when using 7 series FPGA transceivers. Additional cores can be added by continuing to instantiate extra block level modules. One instance of the core is generated with the Include Shared Logic in Core option. This instance contains all the clocking logic that can be shared. The remaining instances can be generated using the Include Shared Logic in Example Design option. This method of using shared logic core is limited to a GT Quad.
To provide the FPGA logic clocks for all core instances,
select a txoutclk port from any transceiver and place it onto global clock
routing using BUFGs; it can be shared across all core instances and transceivers as
illustrated.
Each transceiver and core pair instantiated has its own
independent clock domains synchronous to rxoutclk. These are placed on
BUFMR followed by regional clock routing using a BUFR, as illustrated in the following
figure, and cannot normally be shared across multiple transceivers. The clocking logic for
rxoutclk can only be shared if it is known that the transceiver and core
pairs across QSGMII instances are synchronous.
Zynq 7000 SoC and Kintex 7 Devices
The following figure illustrates sharing clock resources across two instantiations of the core when using 7 series FPGAs transceivers. Additional cores can be added by continuing to instantiate extra block level modules. One instance of the core is generated with the Include Shared Logic in Core option. This instance contains all the clocking logic that can be shared.
The remaining instances can be generated using the Include Shared Logic in Example Design option. This method of using shared logic core is limited to a GT Quad.
To provide the FPGA logic clocks for
all core instances, select a txoutclk port from any
transceiver and place it onto global clock routing using BUFGs; these can be shared across
all core instances and transceivers as illustrated,
Each GTX transceiver and core pair instantiated has its own independent
clock domains synchronous to rxoutclk. These are placed on
global clock routing using a BUFG, as illustrated in the following figure, and cannot be
normally shared across multiple transceivers. The clocking logic for rxoutclk can only be shared if it is known that the transceiver and core pairs
across QSGMII instances are synchronous. In this case the receive clock outputs of clocking
module can be used.
Artix 7 Devices
The following figure illustrates sharing clock resources across two instantiations of the core when using 7 series FPGAs transceivers. Additional cores can be added by continuing to instantiate extra block level modules. One instance of the core is generated with the Include Shared Logic in Core option. This instance contains all the clocking logic that can be shared. The remaining instances can be generated using the Include Shared Logic in Example Design option. The method of using the shared logic core is limited to a GT Quad.
To provide the FPGA logic clocks for all
core instances, select a txoutclk port from any transceiver and place it
onto global clock routing using BUFGs. Pass this clock to an MMCM to generate 125 and 250
MHz clocks. The 125 MHz clock is used to clock the core logic and txusrclk2 of the
transceivers. The 250 MHz clock is used to clock the txusrclk of the
transceivers. These can be shared across all core instances and transceivers as
illustrated.
Each GTP transceiver and core pair
instantiated has its own independent clock domains synchronous to rxoutclk. These are placed on global clock routing using a BUFMR and subdivided
to generate 125 MHz and 250 MHz clocks though BUFRs respectively, as illustrated in the
following figure, and cannot normally be shared across multiple transceivers. The clocking
logic for rxoutclk can only be shared if it is known that
the transceiver and core pairs across QSGMII instances are synchronous. In this case the
receive clock outputs of clocking module can be used. In some devices BUFMRs are not
available and this scheme might not be feasible. Other schemes with a core generated using
the Include Shared Logic in Example Design option
should be considered.
UltraScale and UltraScale+ Devices
The following figure illustrates sharing clock resources across two instantiations of the core when using UltraScale or UltraScale+ device transceivers. Additional cores can be added by continuing to instantiate extra block level modules. One instance of the core is generated with the Include Shared Logic in Core option. This instance contains all the clocking logic that can be shared. The remaining instances can be generated using the Include Shared Logic in Example Design option. This method of using shared logic core is limited to a GT Quad.
To provide the device logic clocks for all
core instances, select a txoutclk port from any transceiver and place it
onto the global clock routing using BUFG_GTs; these can be shared across all core instances
and transceivers as illustrated,
Each transceiver and core pair instantiated has its own
independent clock domains synchronous to rxoutclk. These are placed on the
global clock routing using a BUFG_GT, as illustrated in the following figure, and cannot be
normally shared across multiple transceivers. The clocking logic for
rxoutclk can only be shared if it is known that the transceiver and core
pairs across QSGMII instances are synchronous. In this case the receive clock outputs of
clocking module can be used.