This module creates the sgmii_clk_en clock enable signal for use throughout the SGMII adaptation module.
Clock enabled frequencies are:
• 125 MHz at an operating speed of 1 Gbps
• 12.5 MHz at an operating speed of 100 Mbps
• 1.25 MHz at an operating speed of 10 Mbps
This module also creates output clock sgmii_clk_chx from rise and fall clocks.
Clock generation rise and fall frequencies are:
• 125 MHz at an operating speed of 1 Gbps in PHY mode and for all speeds in MAC mode
• 25 MHz at an operating speed of 100 Mbps
• 2.5 MHz at an operating speed of 10 Mbps
This Figure illustrates the output clock enable signal for the Clock Generation module at 1 Gbps and 100 Mbps speeds.
This Figure also illustrates the formation of the sgmii_clk_r and sgmii_clk_f signals. These are used only in the example design delivered with the core, where they are routed to a device IOB DDR output register. This provides SGMII clock forwarding at the correct frequency.