Block Level HDL - 4.0 English - PG029

The block level contains the following:

• An instance of the QSGMII core
• An instance of a transceiver specific to the target device
• External GMII logic, including IOB and double data rate (DDR) register instances, where required
• An QSGMII adaptation module containing four instances of SGMII adaptation module. Each instance of SGMII adaptation module contains
• The clock management logic required to enable the instance of SGMII operate at 10 Mb/s, 100 Mb/s, and 1 Gb/s.
• GMII logic for both transmitter and receiver paths.
• In MAC mode, the GMII style 8-bit interface is run at 125 MHz for 1 Gb/s operation; 12.5 MHz for 100 Mb/s operation; 1.25 MHz for 10 Mb/s operation.
• In PHY mode, the GMII style 8 bit interface is run at 125 MHz for 1 Gb/s operation; 25 MHz for 100 Mb/s operation; 2.5 MHz for 10 Mb/s operation. For 100/10 Mb/s operation, 4 bits of the MII are mapped to the LSB 4 bits of the GMII style interface.

The block-level HDL connects the PHY side interface of the core to a device-specific transceiver instance and the client side to QSGMII adaptation logic as illustrated in the following figure. This is the most useful part of the example design and should be instantiated in all customer designs that use the core.