Block Level HDL - 3.5 English

Quad Serial Gigabit Media Independent LogiCORE Product Guide (PG029)

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3.5 English

The following files describe the block level for the QSGMII core:





The block level contains the following:

An instance of the QSGMII core

An instance of a transceiver specific to the target device

External GMII logic, including IOB and double data rate (DDR) register instances, where required

An QSGMII adaptation module containing four instances of SGMII adaptation module. Each instance of SGMII adaptation module contains

° The clock management logic required to enable the instance of SGMII operate at 10 Mbps, 100 Mbps, and 1 Gbps.

° GMII logic for both transmitter and receiver paths.

- In MAC mode, the GMII style 8-bit interface is run at 125 MHz for 1 Gbps operation; 12.5 MHz for 100 Mbps operation; 1.25 MHz for 10 Mbps operation.

- In PHY mode, the GMII style 8 bit interface is run at 125 MHz for 1 Gbps operation; 25 MHz for 100 Mbps operation; 2.5 MHz for 10 Mbps operation. For 100/10 Mbps operation, 4 bits of the MII are mapped to the LSB 4 bits of the GMII style interface.

The block-level HDL connects the PHY side interface of the core to a device-specific transceiver instance and the client side to QSGMII adaptation logic as illustrated in This Figure . This is the most useful part of the example design and should be instantiated in all customer designs that use the core.