Block Hierarchy Level Ports

Block Hierarchy Level Ports - 3.5 English

Quad Serial Gigabit Media Independent LogiCORE Product Guide (PG029)

Document ID

PG029

Release Date

2023-11-02

Version

3.5 English

All the ports described here indicate the pins at the block level. The block level design instantiates the core and transceiver. The block level design is expected to be pulled from the IP catalog into the IP Canvas.

This Figure shows the pinout for the QSGMII block with the optional MDIO Management and optional Auto-Negotiation. The port name for multiple instances of an interface is generalized as "CHx." "CHx" takes the value "CH0," "CH1," "CH2," and "CH3."

Figure 2-5: Component Pinout of QSGMII Block with Optional MDIO and Auto-Negotiation
X-Ref Target - Figure 2-5

This Figure shows the pinout for the QSGMII block with only optional MDIO Management. The port name for multiple instances of an interface is generalized as "CHx." "CHx" takes the value "CH0," "CH1," "CH2," and "CH3."

Figure 2-6: Component Pinout of QSGMII Block with Only Optional MDIO Management
X-Ref Target - Figure 2-6

This Figure shows the pinout for the QSGMII block with only optional Auto-Negotiation. The port name for multiple instances of an interface is generalized as "CHx." "CHx" takes the value "CH0," "CH1," "CH2," and "CH3."

Figure 2-7: Component Pinout of QSGMII Block with Only Optional Auto-Negotiation
X-Ref Target - Figure 2-7

This Figure shows the pinout for the QSGMII block without optional MDIO or Auto-Negotiation. The port name for multiple instances of an interface is generalized as "CHx." "CHx" takes the value "CH0," "CH1," "CH2," and "CH3."

Figure 2-8: Component Pinout of QSGMII Block without Optional MDIO or Auto-Negotiation
X-Ref Target - Figure 2-8