The following table shows the relationship between the fields in the AMD Vivado™ IDE and the user parameters (which can be viewed in the Tcl Console).
| Vivado IDE Parameter | User Parameter | Default Value |
|---|---|---|
| Enable MM2S | c_enable_mm2s | 1 |
| Channel type | c_include_mm2s | Full |
| Memory Map Data Width | c_m_axi_mm2s_data_width | 32 |
| Stream data Width | c_m_axis_mm2s_tdata_width | 32 |
| Max burst Size | c_mm2s_burst_size | 16 |
| Width of BTT field | c_mm2s_btt_used | 16 |
| Enable S2MM | c_enable_s2mm | 1 |
| Channel type | c_include_s2mm | Full |
| Memory Map Data Width | c_m_axi_s2mm_data_width | 32 |
| Stream data Width | c_s_axis_s2mm_tdata_width | 32 |
| Max burst Size | c_s2mm_burst_size | 16 |
| Width of BTT field | c_s2mm_btt_used | 16 |
| Enable xCACHE xUSER | c_enable_cache_user | FALSE |
| Enable MM2S Control Signal | c_enable_mm2s_adv_sig | 0 |
| Enable S2MM Control Signal | c_enable_s2mm_adv_sig | 0 |
| Enable Async Clocks | c_mm2s_stscmd_is_async | FALSE |
| Allow Unaligned Transfer | c_include_mm2s_dre | FALSE |
| Enable Store and Forward | c_mm2s_include_sf | TRUE |
| ID Width | c_m_axi_mm2s_id_width | 4 |
| ID Value | c_m_axi_mm2s_arid | 0 |
| Enable Async Clocks | c_s2mm_stscmd_is_async | FALSE |
| Allow Unaligned Transfer | c_include_s2mm_dre | FALSE |
| Enable Store and Forward | c_s2mm_include_sf | TRUE |
| Enable Indeterminate BTT Mode | c_s2mm_support_indet_btt | FALSE |
| ID Width | c_m_axi_s2mm_id_width | 4 |
| ID Value | c_m_axi_s2mm_awid | 0 |
| Address Width (32-64) | c_addr_width | 32 |