Revision History - Revision History - 5.1 English - PG022

AXI DataMover LogiCORE IP Product Guide (PG022)
Document ID
PG022
Release Date
2025-01-09
Version
5.1 English

The following table shows the revision history for this document.

Section Revision Summary
01/09/2026 Version 5.1
Unaligned Transfers Modified the section.
06/11/2025 Version 5.1
General updates Added support for AMD Versal™ Adaptive SoC
04/26/2022 Version 5.1
Product Specification
  • Updated description for Indeterminate BTT Mode.
  • Updated the Command Interface section.
04/05/2017 Version 5.1
Product Specification
  • Updated the description of mm2s_dbg_sel(3:0) in Table 1.
  • Added text to the first paragraph of the Address Posting Control and Status Interface section in Product Specification. The text describes unconnected and connected signals.
11/18/2015 Version 5.1
General updates Added support for UltraScale+ families.
04/01/2015Version 5.1
General updates Added support for 64-bit addressing.
11/19/2014Version 5.1
Product Specification Revised the description of TKEEP Example DataMover Write (S2MM) Timing.
10/01/2014Version 5.1
Product Specification
  • Remove non-incrementing Burst transfers from unsupported features.
  • Minor changes to descriptions in Table 2.
  • Added GUI Parameter to User Parameter Relationship table.
04/02/2014 Version 5.1
General Updates
  • Updated the Clock Frequencies section.
  • Many other minor updates.
12/18/2013 Version 5.1
General Updates Added UltraScale architecture support.
10/02/2013Version 5.1
Product Specification Updated performance numbers in Table 1.
Design Flow Steps
Example Design
General Updates Updated Figure 8-2.
03/20/2013 Version 5.0
Designing with the Core
Design Flow Steps
General Updates
  • Revision number advanced to 5.0 to align with core version number.
  • Updated for Vivado design tools and core version 5.0.
  • Removed all ISE, Virtex 6, and Spartan 6 material.
12/18/2012 Version 2.1
General Updates Updated for Vivado 2012.4 and ISE v14.4 design tools.
Overview
  • Replaced Figure 1-1 with two new figures.
  • Updated max frequency numbers and devices.
Product Specification
  • Removed many rows from resource utilization tables.
  • Removed Allowable Parameter Combinations section.
  • Updated screen captures.
  • Updated output hierarchies.
Debugging Updated Debugging appendix. Updated core version.
10/16/2012 Version 2.0.1
General Updates
  • Updated for Vivado 2012.3 and ISE v14.3.
  • Added MM2S and S2MM block Information
  • Added two figures showing typical use cases for DataMover.
  • Removed AXI Read Master, AXI Write Master sections, AXI DataMover Operation, and Parameter -- I/O Signal Dependencies sections.
Designing with the Core Added two new sections to Designing with the Core :
07/25/2012 Version 2.0
General Updates Updated for Vivado 2012.2, Zynq features, and ISE v14.2
Design Flow Steps Added Vivado content in Customizing and Generating the Core
07/11/2012 Version 1.1
General Updates Template update.
10/19/2011Version 1.0
General Updates Initial Xilinx release.