The following table describes the latency for the AXI DataMover core. Latency is measured in simulation and indicates AXI DataMover core latency cycles exclusive of system dependent latency or throttling.
| Description | Clocks |
|---|---|
| MM2S Channel | |
| Initial m_axi_mm2s_rvalid to m_axis_mm2s_tvalid (Store and Forward disabled) | 1 |
| Initial m_axi_mm2s_rvalid to m_axis_mm2s_tvalid (Store and Forward enabled) | 3 |
| AXI4-Stream packet to packet latency (DRE Disabled) m_axis_mm2s_tlast to m_axis_mm2s_tvalid | 2 |
| AXI4-Stream packet to packet latency (DRE Enabled) m_axis_mm2s_tlast to m_axis_mm2s_tvalid | 3 |
| s_axis_mm2s_cmd_tvalid to m_axi_mm2s_arvalid | 8 |
| S2MM Channel | |
| Initial s_axis_s2mm_tvalid to m_axi_s2mm_awalid (Store and Forward disabled) | 2 |
| Initial s_axis_s2mm_tvalid to m_axi_s2mm_awalid (Store and Forward enabled) | 20 |
| AXI4-Stream packet to packet latency (DRE Disabled) s_axis_s2mm_tlast to s_axis_s2mm_tready | 2 |
| AXI4-Stream packet to packet latency (DRE Enabled) s_axis_s2mm_tlast to s_axis_s2mm_tready | 3 |