|
Core Specifics |
| Supported Device Family
1
|
AMD UltraScale+™
, AMD UltraScale™
, AMD Zynq™ 7000 SoC, 7 series FPGAs, AMD Versal™
Adaptive SoCs |
| Supported User Interfaces |
AXI4, AXI4-Stream
|
| Resources |
See Table 1 and Table 2. |
| Provided with
Core
|
| Design Files |
VHDL |
| Example Design |
VHDL |
| Test Bench |
VHDL |
| Constraints File |
Delivered during IP generation |
| Simulation Model |
Not Provided |
| Supported S/W Driver |
N/A |
| Tested Design Flows
2
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Not Provided |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 47651
|
| All Vivado IP
Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Support web
page
|
- For a complete list of supported devices, see the AMD Vivado™
IP catalog.
- For the supported versions of tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973)
|