Example Design Directory Structure - Example Design Directory Structure - 5.1 English - PG022

AXI DataMover LogiCORE IP Product Guide (PG022)
Document ID
PG022
Release Date
2025-01-09
Version
5.1 English

In the current project directory, a new project with the name <component_name>_example is created and the files are delivered in the <component_name>_example/<component_name>_example.srcs/ directory. This directory and its subdirectories contain all the source files that are required to create the AXI DataMover controller example design.

The following table shows the files delivered as part of example design.

Table 1. Example Design Directory
Name Description
<component_name>_exdes.vhd Top-level HDL file for the example design.
clock_gen.vhd Clock generation module for example design.
axi4_write_master.vhd Read path data generator module for example design.
axis_data_read.vhd Read path data checker module for example design.
axis_write_master.vhd Write path data generator module for example design.
axi_s2mm_read.vhd Write path data checker module for example design.
axis_cmd_gen_mm2s.vhd MM2S Command generator
axis_cmd_gen_s2mm.vhd S2MM Command generator
axis_sts_read.vhd STS data checker

The following table shows the files delivered as part of the test bench.

Table 2. Simulation Directory
Name Description
<component_name>_exdes_tb.vhd Test Bench for the example design

The following table shows the XDC file delivered as part of example design.

Table 3. Constraints Directory
Name Description
<component_name>_exdes.xdc Top level constraints file for the example design.

The XDC delivered with the example design has I/O constraints configured for the KC705 board. These constraints are commented by default. Uncomment the constraints before implementing the example design on KC705 board.