The DataMover operations are controlled by an AXI slave stream interface that receives transfer commands from the user logic. The MM2S and the S2MM each have a dedicated command interface. A command is loaded with a single data beat on the input command stream interface. The width of the command word is normally 72 bits if 32-bit AXI addressing is being used in the system. However, the command word width is extended (by parameterization) if the system address space grows beyond 32 bits. For example, a 64-bit address system requires the command word to be 104 bits wide to accommodate the wider starting address field. The command interface is an AXI4-Stream interface so the total number of bits should be an integer multiple of 8. For example, if the address space is configured as 33 bits, the address portion in the command should be stuffed to make it 40 bits. This is to ensure compliance with the AXI4-Stream protocol. AXI DataMover will internally ignore the stuffed bits.
The format of the command word is shown in the following figure and detailed in the following table. It is the same for either the MM2S or S2MM DataMover elements. The command format allows the specification of a single data transfer from 1-byte to 8,388,607 bytes (7FFFFF hex bytes). A command loaded into the command interface is often referred to as the parent command of a transfer. The DataMover automatically breaks up large transfers into intermediate bursts (child transfers) that comply with the AXI4 protocol requirements.
| Bits | Field Name | Description |
|---|---|---|
|
xUSER | The value written in this field appears on m_axi_mm2s_arcache for MM2S block and m_axi_s2mm_awcache for S2MM block. |
|
xCACHE | The value written in this field appears on m_axi_mm2s_aruser for MM2S block and m_axi_s2mm_awuser for S2MM block. |
|
RSVD | Reserved |
|
TAG | Command TAG: This field is an arbitrary value assigned that is user assigned to the command. The TAG flows through the DataMover execution pipe and gets inserted into the corresponding status word for the command. |
| (N+31) –32 1 | SADDR | Start Address: This field indicates the starting address to use for the memory-mapped side of the transfer requested by the command. If DRE is enabled, the lower order address bits of this field indicate the starting alignment to load on the memory mapped side of the DRE. |
| 31 | DRR | DRE ReAlignment Request: This bit is only used if the optional DRE is included by parameterization. The bit indicates that the DRE alignment needs to be re-established prior to the execution of the associated command. The DRE stream side alignment is derived from the DSA field of the command. The Memory Mapped side alignment is derived from the least significant bits of the SADDR field. |
| 30 | EOF | End of Frame: This bit indicates that the command is an End of Frame command. This generally affects the MM2S element (Read Master) because it causes the stream output logic to assert the TLAST output on the last data beat of the last transfer needed to complete the command. If DRE is included, this also causes the DRE to flush out any intermediate data at the conclusion of the last transfer of the command and submit it to the stream output (in the case of the MM2S Read Master) or to the AXI Write Data Channel (in the case of the S2MM Write Master). This bit should be set for S2MM commands (when the Indeterminate BTT mode is disabled) when TLAST is expected to arrive with the number of bytes programmed in the command. |
| 29 – 24 | DSA |
DRE Stream Alignment: This field is only used by the MM2S
and if the optional MM2S DRE is included by parameterization. The
field is only used when the DRR bit of the associated command is
also set to 1. This 6-bit field indicates the reference alignment of
the MM2S Stream Data Channel for the optional DRE. The value is
byte-lane relative. A value of 0 indicates byte lane 0 (least
significant byte) is the reference byte lane; a value of 1 indicates
byte lane 1, and so on. Valid values are dependent upon the
parameterized data width of the stream data channel. For example, a
32-bit wide data channel has only 4-byte lane positions and thus the
DSA field can only have values of 0 to 3. Note: DRE alignment on the associated memory-mapped
side is derived from the least significant bits of the SADDR
value of the command.
|
| 23 | Type | This field determines the type of AXI4 access. Setting this to 1 enables INCR. A value of 0 enables FIXED address AXI4 transaction. |
| 22 to 0 | BTT | Bytes to Transfer: This 23-bit field indicates the total number of bytes to transfer for the command. Transfers can be from 1 up to 8,388,607 bytes. A value of 0 is not allowed and causes an internal error from the DataMover. The actual number of BTT bits used by the DataMover is controlled by the parameters 'Width of BTT field' for MM2S and S2MM respectively. |
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