Scatter/Gather Mode Register Address Map - Scatter/Gather Mode Register Address Map - 7.1 English - PG021

AXI DMA LogiCORE IP Product Guide (PG021)
Document ID
PG021
Release Date
2025-06-24
Version
7.1 English
Table 1. Scatter/Gather Mode Register Address Map
Address Space Offset 1 Name Description
00h MM2S_DMACR MM2SDMA Control register
04h MM2S_DMASR MM2SDMA Status register
08h MM2S_CURDESC MM2S Current Descriptor Pointer. Lower 32 bits of the address.
0Ch MM2S_CURDESC_MSB MM2S Current Descriptor Pointer. Upper 32 bits of address.
10h MM2S_TAILDESC MM2S Tail Descriptor Pointer. Lower 32 bits.
14h MM2S_TAILDESC_MSB MM2S Tail Descriptor Pointer. Upper 32 bits of address.
2Ch 2 SG_CTL Scatter/Gather User and Cache
30h S2MM_DMACR S2MM DMA Control register
34h S2MM_DMASR S2MM DMA Status register
38h S2MM_CURDESC S2MM Current Descriptor Pointer. Lower 32 address bits
3Ch S2MM_CURDESC_MSB S2MM Current Descriptor Pointer. Upper 32 address bits.
40h S2MM_TAILDESC S2MM Tail Descriptor Pointer. Lower 32 address bits.
44h S2MM_TAILDESC_MSB S2MM Tail Descriptor Pointer. Upper 32 address bits.
  1. Address Space Offset is relative to C_BASEADDR assignment.
  2. Register 2Ch is available only when DMA is configured in multichannel mode.