| Address Space Offset | Name | Description |
|---|---|---|
| 00h | NXTDESC | Bits 5:0 – Reserved Bits 31:6 – Next Descriptor Pointer |
| 04h | NXTDESC_MSB | Provides upper 32 bits of the next descriptor pointer. Applicable when DMA is configured for an address space greater than 32. |
| 08h | BUFFER_ADDRESS | Bits 31:0 – Buffer Address Provides the location of the buffer space available to store data transferred from Stream to Memory Map. The address should be aligned to Memory Map data width. |
| 0Ch | BUFFER_ADDRESS_MSB | Provides the upper 32 bits of buffer address. This is used only when AXI DMA is configured for an address space greater than 32. |
| 10h | CACHE_USER_CTL | Bit 23:0 – Reserved |
| Bit 27:24 – AWCACHE – Cache type. This signal provides additional information about
the cacheable characteristics of the transfer. See the
AMBA®
AXI and ACE Protocol Specification
for a different decoding mechanism. AWCACHE values from RX descriptor are presented on AWCACHE [3:0] bus during address cycle. Default value of this field should be 0011. |
||
| Bits 31:28 – AWUSER – sideband signals used for user- defined information. AWUSER values from RX descriptor are presented on AWUSER [3:0]. AWUSER values and their interpretations are user-defined. You can keep AWUSER static for entire packet by programming same values in all the descriptors within a chain. | ||
| 14h | STRIDE_VSIZE | Bits 15:0 – Stride Control. It is the address distance between the first address of
successive “horizontal” writes. Writes start at the Buffer Address and write HSIZE bytes, then skip STRIDE-HSIZE addresses and write HSIZE bytes, and so on. This continues until VSIZE has been written. On AXI4-Stream this is received on the s_axis_s2mm_ interface as one contiguous packet and is terminated with a single assertion of TLAST on the last data beat of the transfer. |
| Bits 18:16 – Reserved | ||
| Bits 31:19 – Number of “horizontal lines” for stride access. Can represent two-dimensional video data or the size of a 2-D matrix. VSIZE number of transfers, each HSIZE bytes long, are expected to be received for each packet. | ||
| 18h | HSIZE | Bits 15:0 – Number of bytes to transfer in each “horizontal line”
from successive contiguous byte addresses. Can represent a portion
of a video line or a portion of a matrix row when matrix is stored
in row major order. Bits 31:16 – Reserved |
| 1Ch | MC_STS | Multichannel Status bits. Bits 4:0 – TDEST provides routing information for the data stream. TDEST values are static for entire packet. TDEST values are captured from incoming stream and updated in this field. |
| Bits 7:5 – Reserved | ||
| Bits 12:8 – TID provides a stream identifier. TID values are static for entire packet. TID values are captured from incoming stream and updated in this field. | ||
| Bits 15:13 – Reserved | ||
| Bits 19:16 – TUSER – sideband signals used for user-defined information. TUSER values are static for entire packet. TUSER values are captured from incoming stream and updated in this field. | ||
| Bits 25:20 – Reserved | ||
| Bits 25:24 – Reserved | ||
Bit 26 – RXEOP – End of packet flag. It indicates the buffer associated with this
descriptor contains the last part of packet. This flag is set by AXI
DMA.
|
||
Bit 27 – RXSOP – Start of packet flag. It indicates the buffer associated with this
descriptor contains the start of the packet. This flag is set by AXI
DMA.
|
||
Bit 28 – IE – DMA Internal Error due to under-run or over-run conditions.
|
||
Bit 29 – SE – DMA Slave Error. This error occurs if the slave read from the Memory Map
interface issues a Slave Error.
|
||
Bit 30 – DE – DMA Decode Error. This error occurs if the address request is to an
invalid address.
|
||
Bit 31 – Cmp – Completed. This indicates to the software that the DMA engine has
completed the transfer.
|
||
|
||