Programming Sequence - Programming Sequence - 7.1 English - PG021

AXI DMA LogiCORE IP Product Guide (PG021)

Document_ID: PG021
Release_Date: 2025-06-24
Version: 7.1 English

Introduction
Features
IP Facts
Overview
Navigating Content by Design Process
Core Overview
Feature Summary
Applications
Licensing and Ordering
Product Specification
Performance
Resource Use
Port Descriptions
Register Space
Endianess
AXI DMA Register Address Map
Scatter/Gather Mode Register Address Map
Direct Register Mode Register Address Map
Memory Map to Stream Register Detail
Register Access Type Description
MM2S_DMACR (MM2S DMA Control Register – Offset 00h)
MM2S_DMASR (MM2S DMA Status Register – Offset 04h)
MM2S_CURDESC (MM2S DMA Current Descriptor Pointer Register - Offset 08h)
MM2S_CURDES_MSB (MM2S DMA Current Descriptor Pointer Register - Offset 0Ch)
MM2S_TAILDESC (MM2S DMA Tail Descriptor Pointer Register - Offset 10h)
MM2S_TAILDESC_MSB (MM2S DMA Tail Descriptor Pointer Register – Offset 14h)
MM2S_SA (MM2S DMA Source Address Register – Offset 18h)
MM2S_SA_MSB (MM2S DMA Source Address Register – Offset 1Ch)
MM2S_LENGTH (MM2S DMA Transfer Length Register — Offset 28h)
SG_CTL (Scatter/Gather User and Cache Control Register—Offset 2Ch)
Stream to Memory Map Register Detail
S2MM_DMACR (S2MM DMA Control Register – Offset 30h)
S2MM_DMASR (S2MM DMA Status Register – Offset 34h)
S2MM_CURDESC (S2MM DMA Current Descriptor Pointer Register – Offset 38h)
S2MM_CURDESC_MSB (S2MM DMA Current Descriptor Pointer Register – Offset 3Ch)
S2MM_TAILDESC (S2MM DMA Tail Descriptor Pointer Register – Offset 40h)
S2MM_TAILDESC_MSB (S2MM DMA Tail Descriptor Pointer Register – Offset 44h)
S2MM_DA (S2MM DMA Destination Address Register – Offset 48h)
S2MM_DA_MSB (S2MM DMA Destination Address Register – Offset 4Ch)
S2MM_LENGTH (S2MM DMA Buffer Length Register – Offset 58h)
Scatter Gather Descriptor
MM2S_NXTDESC (MM2S Next Descriptor Pointer)
MM2S_NXTDESC_MSB (MM2S Next Descriptor Pointer)
MM2S_BUFFER_ADDRESS (MM2S Buffer Address)
MM2S_BUFFER_ADDRESS_MSB (MM2S Buffer Address)
MM2S_CONTROL (MM2S Control)
MM2S_STATUS (MM2S Status)
MM2S_APP0 to MM2S_APP4
S2MM_NXTDESC (S2MM Next Descriptor Pointer)
S2MM_NXTDESC_MSB (S2MM Next Descriptor Pointer)
S2MM_BUFFER_ADDRESS (S2MM Buffer Address)
S2MM_BUFFER_ADDRESS_MSB (S2MM Buffer Address)
S2MM_CONTROL (S2MM Control)
S2MM_STATUS (S2MM Status)
S2MM_APP0 to S2MM_APP3 (S2MM User Application Fields 0 to 3)
S2MM_APP4 (S2MM User Application Field 4)
Descriptor Management
MM2S Descriptor Settings and AXI Control Stream
AXI Control Stream
S2MM Descriptor Settings and AXI Status Stream
AXI Status Stream
Multichannel DMA Support
Scatter Gather Mode (C_INCLUDE_SG = 1)
MM2S (TX) Descriptor
TX Descriptor Fields
S2MM (RX) Descriptor
RX Descriptor Fields
AXI DMA Multichannel Operation
MM2S
S2MM
2-D Transfers
MM2S
S2MM
Limitations with Multichannel Mode
Register Map for Multichannel (SG = 1)
Designing with the Core
General Design Guidelines
Use the Example Design
Registering Signals
Recognize Timing Critical Signals
Make Only Allowed Modifications
Typical System Interconnect
Clocking
Resets
Programming Sequence
Direct Register Mode (Simple DMA)
Scatter/Gather Mode
Cyclic DMA Mode
Design Flow Steps
Customizing and Generating the Core
Field Descriptions
User Parameters
Output Generation
Constraining the Core
Simulation
Synthesis and Implementation
Example Design
Implementing the Example Design
Simulating the Example Design
Test Bench for the Example Design
Upgrading
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Master Answer Record for the Core
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Hardware Debug
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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