This register provides the Source Address for reading system memory for the Memory Map to Stream DMA transfer.
Figure 1. MM2S_SA Register
| Bits | Field Name | Default Value | Access Type | Description |
|---|---|---|---|---|
| 31 to 0 | Source Address | zeros | R/W | Indicates the source address AXI DMA reads from to transfer data
to AXI4-Stream on the MM2S Channel. Note: If Data Realignment Engine is included,
the Source Address can be at any byte offset. If Data
Realignment Engine is not included, the Source Address must be
MM2S Memory Map data width aligned.
|