Direct Register Mode Register Address Map - Direct Register Mode Register Address Map - 7.1 English - PG021

AXI DMA LogiCORE IP Product Guide (PG021)
Document ID
PG021
Release Date
2025-06-24
Version
7.1 English
Table 1. Direct Register Mode Register Address Map
Address Space Offset 1 Name Description
00h MM2S_DMACR MM2SDMA Control register
04h MM2S_DMASR MM2SDMA Status register
08h– 14h Reserved N/A
18h MM2S_SA MM2S Source Address. Lower 32 bits of address.
1Ch MM2S_SA_MSB MM2S Source Address. Upper 32 bits of address.
28h MM2S_LENGTH MM2STransfer Length (Bytes)
30h S2MM_DMACR S2MM DMA Control register
34h S2MM_DMASR S2MM DMA Status register
38h– 44h Reserved N/A
48h S2MM_DA S2MM Destination Address. Lower 32 bit address.
4Ch S2MM_DA_MSB S2MM Destination Address. Upper 32 bit address.
58h S2MM_LENGTH S2MMBuffer Length (Bytes)
  1. Address Space Offset is relative to C_BASEADDR assignment.