Test Bench Structure - 6.2 English - PG016

The top-level entity is tb_<IP_instance_name>.

It instantiates the following modules:

DUT

The <IP> core instance under test.

axi4lite_mst

The AXI4-Lite master module, which initiates AXI4-Lite transactions to program core registers.

axi4s_video_mst

TheAXI4-Stream master module, which generates ramp data and initiates AXI4-Stream transactions to provide video stimuli for the core and can also be used to open stimuli files and convert them into corresponding AXI4-Stream transactions.

To do this, edit tb_<IP_instance_name>.v:

1. Add define macro for the stimuli file name and directory path

   define STIMULI_FILE_NAME<path><filename>.

2. Comment-out/remove the following line:

   MST.is_ramp_gen(`C_ACTIVE_ROWS, `C_ACTIVE_COLS, 2);

   and replace with the following line:

   MST.use_file(`STIMULI_FILE_NAME);

axi4s_video_slv

The AXI4-Stream slave module, which acts as a passive slave to provide handshake signals for the AXI4-Stream transactions from the core output, can be used to open the data files and verify the output from the core.

To do this, edit tb_<IP_instance_name>.v:

1. Add define macro for the golden file name and directory path

   define GOLDEN_FILE_NAME “<path><filename>”.

2. Comment out the following line:

   SLV.is_passive;

   and replace with the following line:

   SLV.use_file(`GOLDEN_FILE_NAME);

ce_gen

Programmable Clock Enable (ACLKEN) generator.