Register Descriptions - 6.2 English

Table 1. CONTROL Register (Address Offset 0x0000, Access Type: R/W)
Bits	Name	Description
31	SW_RESET	Core reset. Writing a 1 resets the core. This bit automatically clears when reset complete.
30	FSYNC_RESET	Frame Sync Core reset. Writing a 1 resets the core after the start of the next input frame. This bit automatically clears when reset complete.
29:27	RESERVED	Reserved
26	FIELD_ID_POL_SRC	Field ID Polarity Source Select 0: Selects generated polarity from detection register (0x002C) 1: Selects generated polarity from generators register (0x006C)
25	ACTIVE_CHROMA_POL_SRC	Active Chroma Polarity Source Select 0: Selects generated polarity from detection register (0x002C) 1: Selects generated polarity from generator register (0x006C)
24	ACTIVE_VIDEO_POL_SRC	Active Video Polarity Source Select 0: Selects generated polarity from detection register (0x002C) 1: Selects generated polarity from generator register (0x006C)
23	HSYNC_POL_SRC	Horizontal Sync Polarity Source Select 0: Selects generated polarity from detection register (0x002C) 1: Selects generated polarity from generator register (0x006C)
22	VSYNC_POL_SRC	Vertical Sync Polarity Source Select 0: Selects generated polarity from detection register (0x002C) 1: Selects generated polarity from generator register (0x006C)
21	HBLANK_POL_SRC	Horizontal Blank Polarity Source Select 0: Selects generated polarity from detection register (0x002C) 1: Selects generated polarity from generator register (0x006C)
20	VBLANK_POL_SRC	Vertical Blank Polarity Source Select 0: Selects generated polarity from detection register (0x002C) 1: Selects generated polarity from generator register (0x006C)
19	RESERVED	RESERVED
18	CHROMA_SRC	Generator Chroma Polarity and Encoding Source Select 0: Selects Polarity and encoding from detection registers 0x0028 and 0x002C 1: Selects Polarity and encoding from generator registers 0x0068 and 0x006C
17	VBLANK_HOFF_SRC	Generator Vertical Blank Offset Source Select 0: Selects F0_VBLANK_HSTART from detection register (0x003C) selects F0_VBLANK_HEND from detection register (0x003C) 1: Selects F0_VBLANK_HSTART from generator register (0x007C) selects F0_VBLANK_HEND from generator register (0x007C)
16	VSYNC_END_SRC	Generator Vertical Sync End Source Select 0: Selects F0_VSYNC_HEND from detection register (0x0044) selects F0_VSYNC_VEND from detection register (0x0040) 1: Selects F0_VSYNC_HEND from generator register (0x0084) selects F0_VSYNC_VEND from generator register (0x0080)
15	VSYNC_START_SRC	Generator Vertical Sync Start Source Select 0: Selects F0_VSYNC_HSTART from detection register (0x0044) selects F0_VSYNC_VSTART from detection register (0x0040) 1: Selects F0_VSYNC_HSTART from generator register (0x0084) selects F0_VSYNC_VSTART from generator register (0x0080)
14	ACTIVE_VSIZE_SRC	Generator Vertical Active Size Source Select 0: Selects ACTIVE_VSIZE from detection register (0x0020) 1: Selects ACTIVE_VSIZE from generator register (0x0060)
13	FRAME_VSIZE_SRC	Generator Vertical Frame Size Source Select 0: Selects FRAME_VSIZE from detection register (0x0034) 1: Selects FRAME_VSIZE from generator register (0x0074)
12	RESERVED	Reserved
11	HSYNC_END_SRC	Generator Horizontal Sync End Source Select 0: Selects HSYNC_END from detection register (0x0038) 1: Selects HSYNC_END from generator register (0x0078)
10	HSYNC_START_SRC	Generator Horizontal Sync Start Source Select 0: Selects HSYNC_START from detection register (0x0038) 1: Selects HSYNC_START from generator register (0x0078)
9	ACTIVE_HSIZE_SRC	Generator Horizontal Active Size Source Select 0: Selects ACTIVE_HSIZE from detection register (0x0020) 1: Selects ACTIVE_HSIZE from generator register (0x0060)
8	FRAME_HSIZE_SRC	Generator Horizontal Frame Size Source Select 0: Selects FRAME_HSIZE from detection register (0x0030) 1: Selects FRAME_HSIZE from generator register (0x0070)
7:6	RESERVED	Reserved
5	SYNC_ENABLE	Generator Synchronization Enable. Enables the generator to synchronize to the Detector or to the fsync_in pin. 0: Generator does not synchronize 1: Generator synchronizes to the Detector or to fsync_in
4	RESERVED	Reserved
3	DET_ENABLE	Detection Enable. 0: If SW_ENABLE is 0, no detection is performed. All locked status bits are driven Low. SW_ENABLE must be 0 to use the DET_ENABLE bit. If SW_ENABLE is 1, both the detector and generator are enabled. 1: Perform timing signal detection for enabled signals.
2	GEN_ENABLE	Generation Enable. 0: If SW_ENABLE is 0, the generation hardware does not generate video timing output signals. SW_ENABLE must be 0 to use the DET_ENABLE bit. If SW_ENABLE is 1, both the detector and generator are enabled. 1: Enable hardware to generate output. Set this bit High only after the software has configured the generator registers.
1	REG_UPDATE	Register Update. Generator and Fsync Registers are double-buffered. 0: Do not update the Generator and Fsync registers. 1: Update the Generator and Fsync registers at the start of next frame.
0	SW_ENABLE	Core Enable. 0: Generator or Detector can be selectively enabled with bits 2 and 3 of the CONTROL register. 1: Enable both the Video Timing Generator and Detector.

Table 2. STATUS Register (Address Offset 0x0004, Access Type: R/W)
Bits	Name	Description
31:16	FSYNC	Frame Synchronization Interrupt Status. Bits 16-31 are set High when frame syncs 0-15 are set respectively.
15:14	RESERVED	Reserved
13	GEN_ACTIVE_VIDEO	Generated Active Video Interrupt Status. Set High during the first cycle the output active video is asserted.
12	GEN_VBLANK	Generated Vertical Blank Interrupt Status. Set High during the first cycle the output vertical blank is asserted.
11	DET_ACTIVE_VIDEO	Detected Active Video Interrupt Status. Set High during the first cycle the input active video is asserted active after lock.
10	DET_VBLANK	Detected Vertical Blank Interrupt Status. Set High during the first cycle the input vertical blank is asserted active after lock.
9	LOCK_LOSS	Loss-of-Lock Status. Set High when any detection signals have lost locked. Signals that have detection disabled do not affect this bit. Check ERROR (0x0008) Register for signal lock status.
8	LOCK	Lock Status. Set High when all detection signals have locked. Signals that have detection disabled do not affect this bit. Check ERROR (0x0008) Register for signal lock status. The detector typically takes from three to five video frame periods to lock onto the incoming video standard.
7:0	RESERVED	Reserved
Writing a 1 to a bit in the STATUS register clears the corresponding interrupt when set. Writing a 1 to a bit that is cleared, has no effect.

Table 3. ERROR Register (Address Offset 0x0008, Access Type: R/W)
Bits	Name	Description
31:22	RESERVED	Reserved
21	ACTIVE_CHROMA_LOCK	Active Chroma Lock Status. Set High when the active chroma timing remains unchanged.
20	ACTIVE_VIDEO_LOCK	Active Video Lock Status. Set High when the active video timing remains unchanged.
19	HSYNC_LOCK	Horizontal Sync Lock Status. Set High when the horizontal sync timing remains unchanged.
18	VSYNC_LOCK	Vertical Sync Lock Status. Set High when the vertical sync timing remains unchanged.
17	HBLANK_LOCK	Horizontal Blank Lock Status. Set High when the horizontal blank timing remains unchanged.
16	VBLANK_LOCK	Vertical Blank Lock Status Set High when the vertical blank timing remains Unchanged.
15:0	RESERVED	Reserved
Writing a 1 to a bit in the ERROR register clears the corresponding bit when set. Writing a 1 to a bit that is cleared, has no effect.

Table 4. IRQ_ENABLE Register (Address Offset 0x000C, Access Type: R/W)
Bits	Name	Description
31:16	FSYNC	Frame Synchronization Interrupt Enable
15:14	RESERVED	Reserved
13	GEN_ACTIVE_VIDEO	Generated Active Video Interrupt Enable
12	GEN_VBLANK	Generated Vertical Blank Interrupt Enable
11	DET_ACTIVE_VIDEO	Detected Active Video Interrupt Enable
10	DET_VBLANK	Detected Vertical Blank Interrupt Enable
9	LOCK_LOSS	Loss-of-Lock Interrupt Enable
8	LOCK	Lock Interrupt Enable
7:0	RESERVED	Reserved
Setting a bit High in the IRQ_ENABLE register enables the corresponding interrupt. Bits that are Low mask the corresponding interrupt from triggering.

Table 5. VERSION Register (Address Offset 0x0010, Access Type: R)
Bits	Name	Description
31:24	MAJOR	Major version as a hexadecimal value (0x00-0xFF)
23:16	MINOR	Minor version as a hexadecimal value (0x00-0xFF)
15:12	REVISION	Revision as a hexadecimal value (0x0-0xF)
11:8	PATCH_REVISION	Core Revision as a single 4-bit hexadecimal value (0x0-0xF) Used for patch tracking.
7:0	INTERNAL_REVISION	Internal revision number. Hexadecimal value (0x00-0xFF)

Table 6. DETECTOR ACTIVE_SIZE Register (Address Offset 0x0020, Access Type: R)
Bits	Name	Description
31:16	ACTIVE_VSIZE	Detected Vertical Active Frame Size. The height of the frame without blanking in number of lines.
15:0	ACTIVE_HSIZE	Detected Horizontal Active Frame Size. The width of the frame without blanking in number of pixels/clocks.
The maximum supported ACTIVE_HSIZE is less than (Maximum Clocks per Line -1) configured in the Customize IP dialog box. The maximum supported ACTIVE_VSIZE is less than (Maximum Lines per Frame -1) configured in the Customize IP dialog box.

Table 7. DETECTOR TIMING_STATUS Register (Address Offset 0x0024, Access Type: R)
Bits	Name	Description
31:3	RESERVED	Reserved
2	DET_ACTIVE_VIDEO	Detected Active Video Interrupt Status. Set High during the first cycle the input active video is asserted active after lock.
1	DET_VBLANK	Detected Vertical Blank Interrupt Status. Set High during the first cycle the input vertical blank is asserted active after lock.
0	LOCKED	Lock Status. Set High when all detection signals have locked. Signals that have detection disabled do not affect this bit. Check ERROR (0x0008) Register for which signal lock status. The detector typically requires three to five video frame periods to lock onto the incoming video standard. This bit does not latch the lock status, thus, it shows the real-time status of lock as opposed to the LOCKED bit in the Status Register which must be cleared.

Table 8. DETECTOR ENCODING Register (Address Offset 0x0028, Access Type: R)
Bits	Name	Description
31:10	RESERVED	Reserved
9:8	CHROMA_PARITY	Detected Chroma Parity 0: Chroma Active during even active-video lines of frame. Active every pixel of active line 1: Chroma Active during odd active-video lines of frame. Active every pixel of active line 2: Chroma Active during even active video lines of frame. Active every even pixel of active line, inactive every odd pixel 3: Chroma Active during odd active video lines of frame. Active every even pixel of active line, inactive every odd pixel
7	FIELD_ID_PARITY	Detected Field ID Parity 0: Field ID output is currently Low 1: Field ID output is currently High
6	INTERLACED	Detected Progressive/Interlaced 0: Input video format is progressive 1: Input video format is interlaced
5:4	RESERVED	Reserved
3:0	VIDEO_FORMAT	Detected Video Format Denotes when the active_chroma signal is active. 0: YUV 4:2:2 - Active_chroma is active during the same time active_video is active. 1: YUV 4:4:4 - Active_chroma is active during the same time active_video is active. 2: RGB - Active_chroma is active during the same time active_video is active. 3: YUV 4:2:0- Active_chroma is active every other line during the same time active_video is active. See The CHROMA_PARITY bits to control which lines and pixels.

Table 9. DETECTOR POLARITY Register (Address Offset 0x002C, Access Type: R)
Bits	Name	Description
31:7	RESERVED	Reserved
6	FIELD_ID_POL	Detected Field ID Polarity 0: Low during Field 0 and High during Field 1 1: High during Field 0 and Low during Field 1
5	ACTIVE_CHROMA_POL	Detected Active Chroma Polarity 0: active-Low Polarity 1: active-High Polarity
4	ACTIVE_VIDEO_POL	Detected Active Video Polarity 0: active-Low Polarity 1: active-High Polarity
3	HSYNC_POL	Detected Horizontal Sync Polarity 0: active-Low Polarity 1: active-High Polarity
2	VSYNC_POL	Detected Vertical Sync Polarity 0: active-Low Polarity 1: active-High Polarity
1	HBLANK_POL	Detected Horizontal Blank Polarity 0: active-Low Polarity 1: active-High Polarity
0	VBLANK_POL	Detected Vertical Blank Polarity 0: active-Low Polarity 1: active-High Polarity

Table 10. DETECTOR HSIZE Register (Address Offset 0x0030, Access Type: R)
Bits	Name	Description
31:14	RESERVED	Reserved
13:0	FRAME_HSIZE	Detected Horizontal Frame Size. The width of the frame with blanking in number of pixels/clocks.

Table 11. DETECTOR VSIZE Register (Address Offset 0x0034, Access Type: R)
Bits	Name	Description
31:16	FIELD1_VSIZE	Detected Vertical Field 1 Size. The height with blanking in number of lines of field 1.
13:0	FRAME_VSIZE	Detected Vertical Frame or Field 0 Size. The height of the frame with blanking in number of lines.

Table 12. DETECTOR HSYNC Register (Address Offset 0x0038, Access Type: R)
Bits	Name	Description
31:16	HSYNC_END	Detected Horizontal Sync End End cycle index of horizontal sync. Denotes the first cycle hsync_in is deasserted.
15:0	HSYNC_START	Detected Horizontal Sync End Start cycle index of horizontal sync. Denotes the first cycle hsync_in is asserted.

Table 13. DETECTOR F0_VBLANK_H Register (Address Offset 0x003C, Access Type: R)
Bits	Name	Description
31:16	F0_VBLANK_HEND	Detected Vertical Blank Horizontal End End Cycle index of vertical blank. Denotes the first cycle vblank_in is deasserted.
15:0	F0_VBLANK_HSTART	Detected Vertical Blank Horizontal Start Start Cycle index of vertical blank. Denotes the first cycle vblank_in is asserted.

Table 14. DETECTOR F0_VSYNC_V Register (Address Offset 0x0040, Access Type: R)
Bits	Name	Description
31:16	F0_VSYNC_VEND	Detected Vertical Sync Vertical End End Line index of vertical sync. Denotes the first line vsync_in is deasserted.
15:0	F0_VSYNC_VSTART	Detected Vertical Sync Vertical Start Start line index of vertical sync. Denotes the first line vsync_in is asserted.

Table 15. DETECTOR F0_VSYNC_H Register (Address Offset 0x0044, Access Type: R)
Bits	Name	Description
31:16	F0_VSYNC_HEND	Detected Vertical Sync Horizontal End End cycle index of vertical sync. Denotes the first cycle vsync_in is deasserted.
15:0	F0_VSYNC_HSTART	Detected Vertical Sync Horizontal Start Start cycle index of vertical sync. Denotes the first cycle vsync_in is asserted.

Table 16. DETECTOR F1_VBLANK_H Register (Address Offset 0x0048, Access Type: R)
Bits	Name	Description
31:16	F1_VBLANK_HEND	Detected Field 1 Vertical Blank Horizontal End End Cycle index of vertical blank for field 1. Denotes the first cycle vblank_in is deasserted.
15:0	F1_VBLANK_HSTART	Detected Field 1 Vertical Blank Horizontal Start Start Cycle index of vertical blank for field 1. Denotes the first cycle vblank_in is asserted.

Table 17. DETECTOR F1_VSYNC_V Register (Address Offset 0x004C, Access Type: R)
Bits	Name	Description
31:16	F1_VSYNC_VEND	Detected Field 1 Vertical Sync Vertical End End Line index of vertical sync for field 1. Denotes the first line vsync_in is deasserted.
15:0	F1_VSYNC_VSTART	Detected Field 1 Vertical Sync Vertical Start Start line index of vertical sync for field 1. Denotes the first line vsync_in is asserted.

Table 18. DETECTOR F1_VSYNC_H Register (Address Offset 0x0050, Access Type: R)
Bits	Name	Description
31:16	F1_VSYNC_HEND	Detected Field 1 Vertical Sync Horizontal End End cycle index of vertical sync for field 1. Denotes the first cycle vsync_in is deasserted.
15:0	F1_VSYNC_HSTART	Detected Field 1 Vertical Sync Horizontal Start Start cycle index of vertical sync for field 1. Denotes the first cycle vsync_in is asserted.

Table 19. GENERATOR ACTIVE_SIZE Register for Field 0 (Address Offset 0x0060, Access Type: R/W)
Bits	Name	Description
31:16	ACTIVE_VSIZE	Generated Vertical Active Frame Size. The height of the frame without blanking in number of lines.
15:0	ACTIVE_HSIZE	Generated Horizontal Active Frame Size. The width of the frame without blanking in number of cycles¹.
Cycles must be always divisible by pixels per clock. For example, Cycles (Clocks) = Horizontal Resolution/ Pixels per clock.

Table 20. GENERATOR TIMING_STATUS Register (Address Offset 0x0064, Access Type: R)
Bits	Name	Description
31:3	RESERVED	Reserved
2	GEN_ACTIVE_VIDEO	Generated Active Video Interrupt Status. Set High during the first cycle the output active video is asserted.
1	GEN_VBLANK	Generated Vertical Blank Interrupt Status. Set High during the first cycle the output vertical blank is asserted.
0	RESERVED	Reserved

Table 21. GENERATOR ENCODING Register (Address Offset 0x0068, Access Type: R/W)
Bits	Name	Description
31:10	RESERVED	Reserved
9:8	CHROMA_PARITY	Generated Chroma Parity 0: Chroma Active during even active-video lines of frame. Active every pixel of active line 1: Chroma Active during odd active-video lines of frame. Active every pixel of active line 2: Chroma Active during even active video lines of frame. Active every even pixel of active line, inactive every odd pixel 3: Chroma Active during odd active video lines of frame. Active every even pixel of active line, inactive every odd pixel
7	FIELD_ID_PARITY	Generated Field ID Parity 0: Field ID input is currently Low 1: Field ID input is currently High
6	INTERLACED	Generated Progressive/Interlaced 0: Generated video format is progressive 1: Generated video format is interlaced
5:4	RESERVED	Reserved
3:0	VIDEO_FORMAT	Generated Video Format Denotes when the active_chroma signal is active. 0: YUV 4:2:2 - Active_chroma is active during the same time active_video is active. 1: YUV 4:4:4 - Active_chroma is active during the same time active_video is active. 2: RGB - Active_chroma is active during the same time active_video is active. 3: YUV 4:2:0- Active_chroma is active every other line during the same time active_video is active. See The CHROMA_PARITY bits to control which lines and pixels.

Table 22. GENERATOR POLARITY Register (Address Offset 0x006C, Access Type: R/W)
Bits	Name	Description
31:7	RESERVED	Reserved
6	FIELD_ID_POL	Generated Field ID Polarity 0: Low during Field 0 and High during Field 1 1: High during Field 0 and Low during Field 1
5	ACTIVE_CHROMA_POL	Generated Active Chroma Polarity 0: active-Low Polarity 1: active-High Polarity
4	ACTIVE_VIDEO_POL	Generated Active Video Polarity 0: active-Low Polarity 1: active-High Polarity
3	HSYNC_POL	Generated Horizontal Sync Polarity 0: active-Low Polarity 1: active-High Polarity
2	VSYNC_POL	Generated Vertical Sync Polarity 0: active-Low Polarity 1: active-High Polarity
1	HBLANK_POL	Generated Horizontal Blank Polarity 0: active-Low Polarity 1: active-High Polarity
0	VBLANK_POL	Generated Vertical Blank Polarity 0: active-Low Polarity 1: active-High Polarity

Table 23. GENERATOR HSIZE Register (Address Offset 0x0070, Access Type: R/W)
Bits	Name	Description
31:16	RESERVED	Reserved
15:0	FRAME_HSIZE	Generated Horizontal Frame Size. The width of the frame with blanking in number of cycles¹.
Cycles must be always divisible by pixels per clock. For example, Cycles (Clocks) = Horizontal Resolution/ Pixels per clock.

Table 24. GENERATOR VSIZE Register (Address Offset 0x0074, Access Type: R/W)
Bits	Name	Description
31:16	FIELD1_VSIZE	Generated Vertical Field 1 Size. The height with blanking in number of lines of field 1.
15:0	FRAME_VSIZE	Generated Vertical Frame Size. The height of the frame with blanking in number of lines.

Table 25. GENERATOR HSYNC Register (Address Offset 0x0078, Access Type: R/W)
Bits	Name	Description
31:16	HSYNC_END	Generated Horizontal Sync End End cycle index of horizontal sync. Denotes the first cycle hsync_in is deasserted.
15:0	HSYNC_START	Generated Horizontal Sync End Start cycle index of horizontal sync. Denotes the first cycle hsync_in is asserted.

Table 26. GENERATOR F0_VBLANK_H Register (Address Offset 0x007C, Access Type: R/W)
Bits	Name	Description
31:16	F0_VBLANK_HEND	Generated Vertical Blank Horizontal End End Cycle index of vertical blank. Denotes the first cycle vblank_in is deasserted.
15:0	F0_VBLANK_HSTART	Generated Vertical Blank Horizontal Start Start Cycle index of vertical blank. Denotes the first cycle vblank_in is asserted.

Table 27. GENERATOR F0_VSYNC_V Register (Address Offset 0x0080, Access Type: R/W)
Bits	Name	Description
31:16	F0_VSYNC_VEND	Generated Vertical Sync Vertical End End Line index of vertical sync. Denotes the first line vsync_in is deasserted.
15:0	F0_VSYNC_VSTART	Generated Vertical Sync Vertical Start Start line index of vertical sync. Denotes the first line vsync_in is asserted.

Table 28. GENERATOR F0_VSYNC_H Register (Address Offset 0x0084, Access Type: R/W)
Bits	Name	Description
31:16	F0_VSYNC_HEND	Generated Vertical Sync Horizontal End End cycle index of vertical sync. Denotes the first cycle vsync_in is deasserted.
15:0	F0_VSYNC_HSTART	Generated Vertical Sync Horizontal Start Start cycle index of vertical sync. Denotes the first cycle vsync_in is asserted.

Table 29. GENERATOR F1_VBLANK_H Register (Address Offset 0x0088, Access Type: R)
Bits	Name	Description
31:16	F1_VBLANK_HEND	Generated Field 1 Vertical Blank Horizontal End End Cycle index of vertical blank for field 1. Denotes the first cycle vblank_in is deasserted.
15:0	F1_VBLANK_HSTART	Generated Field 1 Vertical Blank Horizontal Start Start Cycle index of vertical blank for field 1. Denotes the first cycle vblank_in is asserted.

Table 30. GENERATOR F1_VSYNC_V Register (Address Offset 0x008C, Access Type: R)
Bits	Name	Description
31:16	F1_VSYNC_VEND	Generated Field 1 Vertical Sync Vertical End End Line index of vertical sync for field 1. Denotes the first line vsync_in is deasserted.
15:0	F1_VSYNC_VSTART	Generated Field 1 Vertical Sync Vertical Start Start line index of vertical sync for field 1. Denotes the first line vsync_in is asserted.

Table 31. GENERATOR F1_VSYNC_H Register (Address Offset 0x0090, Access Type: R)
Bits	Name	Description
31:16	F1_VSYNC_HEND	Generated Field 1 Vertical Sync Horizontal End End cycle index of vertical sync for field 1. Denotes the first cycle vsync_in is deasserted.
15:0	F1_VSYNC_HSTART	Generated Field 1 Vertical Sync Horizontal Start Start cycle index of vertical sync for field 1. Denotes the first cycle vsync_in is asserted.

Table 32. GENERATOR ACTIVE_SIZE Register for Field 1 (Address Offset 0x0094, Access Type: R/W)
Bits	Name	Description
31:16	ACTIVE_VSIZE	Generated Vertical Active Frame Size. The height of the frame without blanking in number of lines.
15:0	ACTIVE_HSIZE	Generated Horizontal Active Frame Size. The width of the frame without blanking in number of cycles¹.
Cycles must be always divisible by pixels per clock. For example, Cycles (Clocks) = Horizontal Resolution/Pixels per clock.

Table 33. FRAME SYNC 0-15 CONFIG Registers (Address Offsets 0x0100-0x013C, Access Type: R/W)
Bits	Name	Description
31:16	V_START	Frame Synchronization Vertical Start Vertical line during which the fsync_out[0] output port is asserted active-High.²
15:0	H_START	Frame Synchronization Horizontal Start Horizontal Cycle during which fsync_out[0] output port is asserted active-High
Frame Sync 1-15 Config Registers (address offset 0x0100–0x013C) have the same format as the Frame Sync 0 Config Register. Frame Syncs are not active during the complete line, only in the cycle during which both the V_START and H_START are valid each frame.

Table 34. Generator Global Delay Register (Address Offset 0x140, , Access Type: R/W)
Bits	Name	Description
31:16	V_DELAY	Generator Vertical Delay Vertical line offset. This is the number of lines that the generated output that shifts relative to the detector (input timing). The vertical delay is only available when both the detector and generator are enabled. Can be combined with the H_DELAY.
15:0	H_DELAY	Generator Horizontal Delay Horizontal cycle offset. This is the number of clock cycles that the generated output that shifts relative to the detector (input timing). The horizontal delay is only available when both the detector and generator are enabled. Can be combined with the V_DELAY.

Register Descriptions - 6.2 English - PG016

Video Timing Controller LogiCORE IP Product Guide (PG016)