The VTC core has two reset sources: RESETn pin
(hardware reset), and software reset provided via the AXI4-Lite control interface (when present). The software reset is available via the Control Register at
address offset 0x0000, Bit [31].
RESETn is not synchronized
internally to the video timing processing. Deasserting RESETn while frame timing
is being process can lead to incomplete frames (from the generator).The external reset pulse needs to be held for at least 32 CLK cycles to reset the core. The
RESETn signal only resets the video timing interfaces and processing of the
core. The AXI4-Lite interface is unaffected by the
RESETn signal to allow the video timing processing core to be reset without
halting the AXI4-Lite interface.
However, if the RESETn is asserted Low during an AXI4-Lite register read or write, the AXI4-Lite
interface asserts the slave error response (0x2) for all addresses.