Frame Syncs - 6.2 English - PG016

Video Timing Controller LogiCORE IP Product Guide (PG016)

Document ID
PG016
Release Date
2025-11-26
Version
6.2 English

The VTC has a frame synchronization output bus. Each bit can be configured to toggle High for any one clock cycle during each video frame. Each bit is independently configured for horizontal and vertical clock cycle position with the Frame Sync Configuration Registers (address offsets 0x0100 to 0x013C).