Frame Sync Position Tab - 6.2 English - PG016

Video Timing Controller LogiCORE IP Product Guide (PG016)
Document ID
PG016
Release Date
2025-11-26
Version
6.2 English
Figure 1. Frame Sync Position Tab
Frame Sync # Horizontal Position
Sets the default value of the clock cycle count during which Frame Sync # is active in the FRAME SYNC 0-15 CONFIG registers at address offset 0x100 to 0x13C.
Frame Sync # Vertical Position
Sets the default value of the line count during which Frame Sync # is active in the FRAME SYNC 0-15 CONFIG registers at address offset 0x100 to 0x13C.
Note: The parameter values within the Constant/Default Timing Generation Options are also the values used during timing generation when the Include AXI4-Lite Register Interface parameter is disabled. These parameter values are used when the core is in constant mode when it does not have an AXI4-Lite interface. The default values for the resolutions are set as per CTA-861-H.