Default/Constant Tab - 6.2 English - PG016

Video Timing Controller LogiCORE IP Product Guide (PG016)

Document ID
PG016
Release Date
2025-11-26
Version
6.2 English
Figure 1. Default/Constant Tab

Video Format
Video Mode
Sets the default video format and controls the Horizontal, Vertical, and Horizontal Fine Adjustment settings below. Values of 720p, 480p, 1080p, or Custom are valid. The interlaced video modes of 1080i, 480i, and 576i are also available when the Interlaced Support parameter is checked. Video Modes are removed or added to this list based upon the sizes selected in the Max Clocks per Line and Max Lines per Frame parameters.
Chroma Format
Sets the default value of the video format in the GENERATOR ENCODING register at address offset 0x68. This controls the behavior of the active_chroma_out output port.
Chroma Parity
Sets the default value of the chroma parity in the GENERATOR ENCODING register at address offset 0x68. This controls the behavior of the active_chroma_out output port.
Horizontal Settings
Active Size
Sets the default number of clock cycles per frame (without blanking) in the GENERATOR ACTIVE_SIZE register at address offset 0x060.
Frame Size
Sets the default number of clock cycles per frame (with blanking) in the GENERATOR HSIZE register at address offset 0x70.
Sync Start
Sets the default value of the clock cycle count during which the horizontal sync starts in the GENERATOR HSYNC register at address offset 0x78.
Sync End
Sets the default value of the clock cycle count during which the horizontal sync ends in the GENERATOR HSYNC register at address offset 0x78.
Frame/Field 0 Vertical Settings
Active Size
Sets the default number of lines per frame (without blanking) in the GENERATOR ACTIVE_SIZE register at address offset 0x060.
Frame Size
Sets the frame/field 0 default number of lines per frame size (with blanking) in the GENERATOR VSIZE register at address offset 0x74, bits 12:0.
Sync Start
Sets the default value of the line count during which the vertical sync starts in the GENERATOR F0_VSYNC_V register at address offset 0x80.
Sync End
Sets the default value of the line count during which the vertical sync ends in the GENERATOR F0_VSYNC_V register at address offset 0x80.
Frame/Field 0 Horizontal Fine Adjustment
Vblank Start
Sets the default value of the clock cycle count during which the vertical blank starts in the GENERATOR F0_VBLANK_H register at address offset 0x7C.
Vblank End
This parameter sets the default value of the clock cycle count during which the vertical blank ends in the GENERATOR F0_VBLANK_H register at address offset 0x7C.
VSync Start
This parameter sets the default value of the clock cycle count during which the vertical sync starts in the GENERATOR F0_VSYNC_H register at address offset 0x84.
Vsync End
This parameter sets the default value of the clock cycle count during which the vertical sync ends in the GENERATOR F0_VSYNC_H register at address offset 0x84.
Field 1 Vertical Settings
Interlaced
Enables generating interlaced video and sets the Interlaced bit (6) in the GENERATOR ENCODING register to 1. This parameter is only available when the Interlaced Video Support parameter is enabled.
Frame Size
Sets the Field 1 default number of lines per frame size (with blanking) in the GENERATOR VSIZE register at address offset 0x74, bits 28:16.
Sync Start
Sets the Field 1 default value of the line count during which the vertical sync starts in the GENERATOR F1_VSYNC_V register at address offset 0x8C.
Sync End
Sets the Field 1 default value of the line count during which the vertical sync ends in the GENERATOR F1_VSYNC_V register at address offset 0x8C.
Field 1 Horizontal Fine Adjustment
Vblank Start
Sets the Field 1 default value of the clock cycle count during which the vertical blank starts in the GENERATOR F1_VBLANK_H register at address offset 0x88.
Vblank End
Sets the Field 1 default value of the clock cycle count during which the vertical blank ends in the GENERATOR F1_VBLANK_H register at address offset 0x88.
VSync Start
Sets the Field 1 default value of the clock cycle count during which the vertical sync starts in the GENERATOR F1_VSYNC_H register at address offset 0x90.
Vsync End
Sets the Field 1 default value of the clock cycle count during which the vertical sync ends in the GENERATOR F1_VSYNC_H register at address offset 0x90.
Active Polarity
Field ID
Sets the polarity of the field_id_out signal. Values of Active High or Active Low are valid. This parameter is enabled when the Interlaced Video Support and Interlaced parameters are enabled.
Vblank
Sets the polarity of the vblank_out signal. Values of Active High or Active Low are valid.
Hblank
Sets the polarity of the hblank_out signal. Values of Active High or Active Low are valid.
Vsync
Sets the polarity of the vsync_out signal. Values of Active High or Active Low are valid.
Hsync
Sets the polarity of the hsync_out signal. Values of Active High or Active Low are valid.
Active Video
Sets the polarity of the active_video_out signal. Values of Active High or Active Low are valid.
Active Chroma
Sets the polarity of the active_chroma_out signal. Values of Active High or Active Low are valid.