This section contains information about constraining the core in the Vivado Design Suite.
Required Constraints
The only constraints required are clock frequency constraints for the video
clock, clk, and the AXI4-Lite clock, s_axi_aclk. Paths between the
two clock domains must be constrained with a max_delay
constraint and use the datapathonly flag, causing setup and
hold checks to be ignored for signals that cross clock domains. These constraints are
provided in the XDC constraints file included with the core.
Device, Package, and Speed Grade Selections
This section is not applicable for this IP core.
Clock Frequencies
This section is not applicable for this IP core.
Clock Management
This section is not applicable for this IP core.
Clock Placement
This section is not applicable for this IP core.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
This section is not applicable for this IP core.