The signals not included in the AXI4-Lite interface are specified in the following table.
| Name | I/O | Width | Description |
|---|---|---|---|
| clk | I | 1 | Video Core Clock |
| clken | I | 1 | Video Core active-High Clock Enable |
| det_clken | I | 1 | Video Timing Detection Core active-High Clock Enable |
| gen_clken | I | 1 | Video Timing Generator Core active-High Clock Enable |
| resetn | I | 1 | Video Core active-Low Synchronous Reset |
| irq | O | 1 | Interrupt request output, active-High edge |
| intc_if | O | 32 | OPTIONAL EXTERNAL INTERRUPT CONTROLLER INTERFACE Available when the "Include INTC Interface" or C_HAS_INTC_IF has been selected. Bits [31:8] are the same as the bits [31:8] in the status register (0x0004). Bits [5:0] are the same as bits [21:16] of the error register (0x0008). Bits [7:6] are reserved and are always 0. |
| Detector Interface (Video Timing Input Interface) | |||
| field_id_in | I | 1 | INPUT FIELD ID Used to set the field_id polarity in the Detector Polarity Register (Address Offset 0x002C). Optional. Only valid when interlace support and field id are enabled. |
| hsync_in | I | 1 | INPUT HORIZONTAL SYNCHRONIZATION Used to set the DETECTOR HSYNC register. Polarity is auto-detected. Optional. Either horizontal blank or horizontal synchronization signal inputs must be present. Both do not have to be present. If the hsync_in input is not connected, the "Horizontal Sync Detection" option must be deselected. |
| hblank_in | I | 1 | INPUT HORIZONTAL BLANK Used to set the DETECTOR HSIZE register. Polarity is auto-detected. Optional. Either horizontal blank or horizontal synchronization signal inputs must be present. Both do not have to be present. If the hblank_in input is not connected, the "Horizontal Blank Detection" option must be deselected. |
| vsync_in | I | 1 | INPUT VERTICAL SYNCHRONIZATION Used to set the DETECTOR F0_VSYNC_V and the F0_VSYNC_H registers. Polarity is auto-detected. Optional. One of the following inputs must be present: active video, vertical blank, or vertical synchronization. If the vsync_in input is not connected, the "Vertical Sync Detection" option must be deselected. |
| vblank_in | I | 1 | INPUT VERTICAL BLANK Used to set the DETECTOR_VSIZE and the F0_VBLANK_H registers. Polarity is auto-detected. Optional. One of the following inputs must be present: active video, vertical blank, or vertical synchronization. If the vblank_in input is not connected, the "Vertical Blank Detection" option must be deselected. |
| active_video_in | I | 1 | INPUT ACTIVE VIDEO Used to set the DETECTOR ACTIVE_SIZE register. Polarity is auto-detected. Optional. One of the following inputs must be present: active video, vertical blank, or vertical synchronization. If the active_video_in input is not connected, the "Active Video Detection" option must be deselected. |
| active_chroma_in | I | 1 | INPUT ACTIVE CHROMA Used to set the VIDEO_FORMAT and the CHROMA_PARITY bits in the Detector Encoding Register. Polarity is auto-detected. Optional. If the active_chroma_in input is not connected, the "Active Chroma Detection" option must be deselected. |
| Generator Interface (Video Timing Output Interface) | |||
| field_id_out | O | 1 | OUTPUT FIELD ID Generated field ID signal. Polarity configured by the Generator Polarity Register (Address Offset 0x006C). Optional. Only enabled when interlaced support and field ID generation is enabled. |
| hsync_out | O | 1 | OUTPUT HORIZONTAL SYNCHRONIZATION Generated horizontal synchronization signal. Polarity configured by the control register. Asserted active during the cycle set by the HSYNC_START bits and deasserted during the cycle set by the HSYNC_END bits in the GENERATOR HSYNC register. |
| hblank_out | O | 1 | OUTPUT HORIZONTAL BLANK Generated horizontal blank signal. Polarity configured by the control register. Asserted active during the cycle set by ACTIVE_HSIZE and deasserted during the cycle set by the FRAME_HSIZE bits in the GENERATOR HSIZE register. |
| vsync_out | O | 1 | OUTPUT VERTICAL SYNCHRONIZATION Generated vertical synchronization signal. Polarity configured by the control register. Asserted active during the line set by the F#_VSYNC_VSTART bits and deasserted during the line set by the F#_VSYNC_VEND bits in the GENERATOR F#_VSYNC_V registers. |
| vblank_out | O | 1 | OUTPUT VERTICAL BLANK Generated vertical blank signal. Polarity configured by the control register. Asserted active during the line set by the ACTIVE_VSIZE bits and deasserted during the line set by the GENERATOR VSIZE register. |
| active_video_out | O | 1 | OUTPUT ACTIVE VIDEO Generated active video signal. Polarity configured by the control register. Active for non blanking lines. Asserted active during the first cycle of the field/frame and deasserted during the cycle set by the GENERATOR ACTIVE_SIZE register |
| active_chroma_out | O | 1 | OUTPUT ACTIVE CHROMA Generated active chroma signal. Denotes which lines contain valid chroma samples (used for YUV 4:2:0). Polarity configured by the GENERATOR POLARITY register. Active for non-blanking lines configured y the VIDEO_FORMAT and the CHROMA_PARITY bits in the GENERATOR Encoding Register. |
| Frame Synchronization Interface | |||
| fsync_out | O | [Frame Syncs - 1:0] | FRAME SYNCHRONIZATION OUTPUT Each Frame Synchronization bit toggles for only one clock cycle during each frame. The number of bits is configured with the Frame Syncs GUI parameter. Each bit is independently configured for horizontal and vertical clock cycle position with the Frame Sync 0-15 Config registers). |
| fsync_in | I | 1 | FRAME SYNCHRONIZATION INPUT This is a one clock cycle pulse (active-High) input. The video timing generator synchronizes to the input if used. |
| sof_state | I | 1 | Indicates AXI4-Stream start of Frame. When used with the AXI4 Video Out bridge, connect the sof_state output port of the bridge to the input sof_state of VTC. |
|
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The clk, clken, resetn,
det_clken, and gen_clken signals are shared between the
core and the Video Timing interfaces. The AXI4-Lite
control interface has its own set of clock, clock enable, and reset pins:
S_AXI_ACLK, S_AXI_ACLKEN, and
S_AXI_ARESETn.