|
Core Specifics |
| Supported Device Family
1
|
Versal™
,
UltraScale™
,
UltraScale+™
2
|
| Supported User Interfaces |
AXI4-Stream
|
| Resources |
For details about performance
and resource use, see ieee802d3-200g-rs-fec.html
. |
| Provided with Core
|
| Design Files |
Encrypted RTL |
| Example Design |
N/A |
| Test Bench |
Not Provided |
| Constraints File |
Xilinx Constraints File |
| Simulation Model |
Encrypted Verilog |
| Supported S/W Driver |
N/A |
| Tested Design Flows
3
|
| Design Entry |
Vivado® Design Suite
|
| Simulation |
For supported simulators, see the
Xilinx Design Tools: Release Notes
Guide. |
| Synthesis |
Vivado® Design Suite
|
| Support |
| All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
|
Xilinx
Support web page
|
- For a complete list of supported devices, see
the
Vivado®
IP catalog.
- -1 speed grades are not supported for these
devices.
- For the supported versions of third-party
tools, see the
Xilinx Design Tools: Release Notes
Guide.
|