IP Facts - 3.0 English

O-RAN Radio Interface O-RAN Radio Interface (PB063)

Document ID
PB063
Release Date
2023-05-17
Version
3.0 English
LogiCORE IP Facts Table
Core Specifics
Supported Device Family 1 3 AMD Versal™ adaptive SoC, AMD Kintex™ UltraScale+™ , AMD Virtex™ UltraScale+™ , AMD Zynq™ UltraScale+™ MPSoC, AMD Zynq™ UltraScale+™ RFSoC, AMD Kintex™ UltraScale™ , AMD Virtex™ UltraScale™
Supported User Interfaces AXI4-Stream
Resources Performance and Resource Use web page (registration required)
Provided with Core
Design Files Encrypted RTL
Example Design Verilog
Test Bench Verilog
Constraints File Xilinx Design Constraints (XDC)
Simulation Model Verilog
Supported S/W Driver Linux user space driver (Libmetal)
Tested Design Flows 2
Design Entry AMD Vivado™ Design Suite
Simulation For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
Synthesis Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: 73648
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Support web page
  1. For a complete list of supported devices, see the Vivado IP catalog.
  2. For the supported versions of the tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
  3. A -2 or faster speed grade is required for 25G operation.