IP Facts - 1.0 English

XDMA/QDMA Simulation (PB062)

Document ID
Release Date
1.0 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 UltraScale+™
Supported User Interfaces AXI4-Stream
Resources N/A
Provided with Core
Design Files N/A
Example Design N/A
Test Bench N/A
Constraints File N/A
Simulation Model Simulation only IP
Supported S/W Driver Check Xilinx Runtime for emulation driver
Tested Design Flows 2
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis N/A
Release Notes and Known Issues N/A
All Vivado IP Change Logs Master Vivado IP Change Logs: 72275
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.
  2. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.