| Parameter Name | Description | Format (Default Value) |
|---|---|---|
| C_M_AXIS_TUSER_WIDTH | User width for Master AXI4-Stream interface | Long (1) |
| C_M_AXIS_TID_WIDTH | ID width for Master AXI4-Stream interface | Long (1) |
| C_M_AXIS_TDEST_WIDTH | DEST width for Master AXI4-Stream interface | Long (1) |
| C_S_AXIS_TUSER_WIDTH | User width for Slave AXI4-Stream interface | Long (1) |
| C_S_AXIS_TID_WIDTH | ID width for Slave AXI4-Stream interface | Long (1) |
| C_S_AXIS_TDEST_WIDTH | DEST width for slave AXI4-Stream interface | Long (1) |
| C_M_AXIMM_TARGET_SLAVE_BASE_ADDR | Base address of targeted slave | BitString (0x40000000) |
| C_M_AXIMM_BURST_LEN | Burst Length supports 1, 2, 4, 8, 16, 32, 64, 128, 256 | List(16) |
| C_M_AXIMM_ID_WIDTH | Thread ID width | Long (1) Maximum: 32 Minimum: 0 |
| C_M_AXIMM_DATA_WIDTH | Width of data bus | Long (32) |
| C_M_AXIMM_ADDR_WIDTH | Width of address bus | Long (32) |
| C_M_AXIMM_AWUSER_WIDTH | Width of user write address bus | Long (1) Maximum:1024 Minimum:0 |
| C_M_AXIMM_ARUSER_WIDTH | Width of user read address bus | Long (1) Maximum:1024 Minimum:0 |
| C_M_AXIMM_WUSER_WIDTH | Width of user write data bus | Long (1) Maximum:1024 Minimum:0 |
| C_M_AXIMM_RUSER_WIDTH | Width of user read data bus | Long (1) Maximum:1024 Minimum:0 |
| C_M_AXIMM_BUSER_WIDTH | Width of user response bus | Long (1) Maximum:1024 Minimum:0 |
| C_S_AXIS_TDATA_WIDTH | AXI4-Stream sink; data width | Long (32) |
| C_M_AXIS_TDATA_WIDTH | Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH | Long (32) |
| C_M_AXIS_START_COUNT | Start count is the number of clock cycles the master waits before initiating/issuing any transaction | Long (32) |
| C_M_AXIMM_AUX_TARGET_SLAVE_BASE_ADDR | Base address of targeted slave | BitString (0x40000000) |
| C_M_AXIMM_AUX_BURST_LEN | Burst length supports 1, 2, 4, 8, 16, 32, 64, 128, 256 | List(16) |
| C_M_AXIMM_AUX_ID_WIDTH | Thread ID width | Long (1) Maximum: 32 Minimum: 0 |
| C_M_AXIMM_AUX_DATA_WIDTH | Width of data bus | Long (32) |
| C_M_AXIMM_AUX_ADDR_WIDTH | Width of address bus | Long (32) |
| C_M_AXIMM_AUX_AWUSER_WIDTH | Width of user write address bus | Long (1) Maximum:1024 Minimum:0 |
| C_M_AXIMM_AUX_ARUSER_WIDTH | Width of user read address bus | Long (1) Maximum:1024 Minimum:0 |
| C_M_AXIMM_AUX_WUSER_WIDTH | Width of user write data bus | Long (1) Maximum:1024 Minimum:0 |
| C_M_AXIMM_AUX_RUSER_WIDTH | Width of user read data bus | Long (1) Maximum:1024 Minimum:0 |
| C_M_AXIMM_AUX_BUSER_WIDTH | Width of user Response bus | Long (1) Maximum:1024 Minimum:0 |
| C_M_AXICTRL_DATA_WIDTH | Width of M_AXI data bus. The master issues write data and accepts read data where the width of the data bus is C_M_AXI_DATA_WIDTH |
Long (32) |
| C_M_AXICTRL_TARGET_SLAVE_BASE_ADDR | The master requires a target slave base address. The master initiates read and write transactions on the slave with the base address specified here as a parameter | bitString (0x40000000) |
| C_M_AXICTRL_START_DATA_VALUE | The master starts generating data from the C_M_START_DATA_VALUE value | bitString (0xAA000000) |
| C_M_AXICTRL_ADDR_WIDTH | Width of M_AXI address bus. The master generates the read and write addresses of width specified as C_M_AXI_ADDR_WIDTH. |
Long (32) |
| C_M_AXICTRL_TRANSACTIONS_NUM | Transaction number is the number of write and read transactions the master will perform as a part of this example memory test. | Long (4) |
| C_STM_ITF_ENABLE | Enables AXI4-Stream interfaces. | Bool (false) |
| C_M_AXIMM_AUX_ENABLE | Enables AUX interfaces. | Bool (false) |
| USE_LEGACY_FMODEL | Use legacy model | Bool (True) |