IP Facts - 1.0 English

Programmable Logic I/O Simulation: Slave (PB060)

Document ID
Release Date
1.0 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 Versal™ ACAP
Supported User Interfaces AXI4-Stream
Resources N/A
Provided with Core
Design Files N/A
Example Design N/A
Test Bench N/A
Constraints File N/A
Supported S/W Driver None
Tested Design Flows 2
Design Entry Vivado® Design Suite
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.
  2. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide