Xil_DCacheInvalidateRange - Xil_DCacheInvalidateRange - 2026.1 English - UG643

Invalidate the Data cache for the given address range.

If the bytes specified by the address range are cached by the Data cache, the cachelines containing those bytes are invalidated. If the cachelines are modified (dirty), the modified contents are lost and are not written to the system memory before the lines are invalidated.

In this function, if start address or end address is not aligned to cache-line, particular cache-line containing unaligned start or end address is flush first and then invalidated the others as invalidating the same unaligned cache line results into loss of data. This issue raises few possibilities.

If the address to invalidate is not cache-line aligned, the following choices are available:

1. Invalidate the cache line when required but it can result in hard-to-debug issues. If some other variable are allocated in the same cache line and are recently updated (in cache), the invalidation results in loss of data.
2. Flush the cache line first to ensure that if any other variable present in the same cache line and updated recently are flushed out to memory. Then it can safely be invalidated. Again it sounds good, but this can result in issues. For example, when the invalidation happens in a typical ISR (after a DMA transfer has updated the memory), then flushing the cache line means, losing data that were updated recently before the ISR got invoked.

Linux prefers the second one. To have uniform implementation (across standalone and Linux), the second option is implemented. With this case, ensure the following:

1. Whenever possible, the addresses must be cache line aligned. Ensure that not only start address but the end address is also cache line aligned.
2. Avoid situations where invalidation is required after the data is updated by peripheral/DMA directly into the memory. It is not tough to achieve (but it is risky). The common use case to do invalidation is when a DMA happens. Generally for such use cases, buffers can be allocated first and then start the DMA. The practice to follow here is that immediately after buffer allocation and before starting the DMA, perform the invalidation. With this approach, invalidation is not required after the DMA transfer is over.

This works if executed carefully. However, there is no guarantee that invalidate is not required after DMA is complete. For example, if the first cache line or last cache line (assuming the buffer in question comprises of multiple cache lines) are available into cache (between the time it is invalidated and DMA completes) due of speculative prefetching or reading data for a variable present in the same cache line, then is is required to invalidate the cache after DMA is complete.

Prototype

void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);

Parameters

The following table lists the Xil_DCacheInvalidateRange function arguments.

Returns

None.