XilPM API Version Detail - XilPM API Version Detail - 2026.1 English - UG643

Standalone Library Documentation: BSP and Libraries Document Collection (UG643)
Document ID
UG643
Release Date
2026-06-23
Version
2026.1 English

XilPM EEMI API Version Detail

This section provide details of EEMI API version and the history for PM APIs of XilPM library.

Table 1. XilPM EEMI API Version Detail
Name ID Platform Version Description
PM_GET_API_VERSION 0x1 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to request the version number of the API.
PM_SET_CONFIGURATION 0x2 Zynq UltraScale+ MPSoC 1 The API is used to configure the power management framework.
Note: Deprecated in Versal but supported in Zynq UltraScale+ MPSoC.
PM_GET_NODE_STATUS 0x3 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 2 V1 - The API is used to obtain information about current status of a device.
V2 - Added support to get proper state value for halt state.
PM_GET_OP_CHARACTERISTIC 0x4 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 2 V1 - The API is used to get operating characteristics of a device.
V2 - Added support of bitmask functionality; user can check the supported type first before performing the actual functionality.
PM_REGISTER_NOTIFIER 0x5 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 3 V1 - The API is used to register a subsystem to be notified about the device event.
V2 - Added support of event management functionality.
Note: V2 is supported in Versal but Zynq UltraScale+ MPSoC supports only V1.
V3 - Added support to unregister all notifiers at once.
PM_REQUEST_SUSPEND 0x6 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to send suspend request to another subsystem.
PM_SELF_SUSPEND 0x7 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 3 V1 - The API is used to suspend a child subsystem.
V2 - Added support of cpu idle functionality during force powerdown.
V3 - Added support of CPU off state.
Note: V3 is supported in Versal but Zynq UltraScale+ MPSoC supports only V1.
PM_FORCE_POWERDOWN 0x8 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 2 V1 - The API is used to powerdown other processor or node.
V2 - Added support of cpu idle functionality during force powerdown.
Note: V2 is supported in Versal but Zynq UltraScale+ MPSoC supports only V1.
PM_ABORT_SUSPEND 0x9 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used by a subsystem to abort suspend of a child subsystem.
PM_REQUEST_WAKEUP 0xA Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to start-up and wake-up a child subsystem.
PM_SET_WAKEUP_SOURCE 0xB Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to set wakeup source.
PM_SYSTEM_SHUTDOWN 0xC Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to shutdown or restart the system.
PM_REQUEST_NODE 0xD Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 2 V1 - The API is used to request the usage of a device.
V2 - Added support of security policy handling during request device.
Note: V2 is supported in Versal but Zynq UltraScale+ MPSoC supports only V1.
PM_RELEASE_NODE 0xE Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 3 V1 - The API is used to release the usage of a device.
V2 - Added support of security policy handling during request device.
Note: V2 is supported in Versal but Zynq UltraScale+ MPSoC supports only V1.
V3 - Added support for bulk device release.
PM_SET_REQUIREMENT 0xF Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to announce a change in requirement for a specific slave node which is currently in use.
PM_SET_MAX_LATENCY 0x10 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to set maximum allowed latency for the device.
PM_RESET_ASSERT 0x11 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to reset or de-reset a device.
PM_RESET_GET_STATUS 0x12 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to read the device reset state.
PM_MMIO_WRITE 0x13 Zynq UltraScale+ MPSoC 1 The API is used to write a value into a register.
Note: Deprecated in Versal but supported in Zynq UltraScale+ MPSoC.
PM_MMIO_READ 0x14 Zynq UltraScale+ MPSoC 1 The API is used to read a value from a register.
Note: Deprecated in Versal but supported in Zynq UltraScale+ MPSoC.
PM_INIT_FINALIZE 0x15 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to initialize subsystem and release unused devices.
PM_GET_CHIPID 0x18 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to request the version and ID code of a chip.
PM_PINCTRL_REQUEST 0x1C Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to request the pin.
PM_PINCTRL_RELEASE 0x1D Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to release the pin.
PM_PINCTRL_GET_FUNCTION 0x1E Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to read the pin function.
PM_PINCTRL_SET_FUNCTION 0x1F Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to set the pin function.
PM_PINCTRL_CONFIG_PARAM_GET 0x20 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to read the pin parameter value.
PM_PINCTRL_CONFIG_PARAM_SET 0x21 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 2 V1 - The API is used to set the pin parameter value.
V2 - Added support of MIO tri-state controlling functionality.
Note: V2 is supported in Zynq UltraScale+ MPSoC but Versal supports only V1.
PM_IOCTL 0x22 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 3 V1 - The API is used to perform driver-like IOCTL functions on shared system devices.
V2 - Added support of bitmask functionality; user can check the supported ID first before performing the actual functionality.
V3 - Add support of zeroization of AIE data and program memory separately.
Note: V3 is supported in Versal but Zynq UltraScale+ MPSoC supports only V2.
PM_QUERY_DATA 0x23 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 2 V1 - The API is used to query information about the platform resources.
V2 - Added support of bitmask functionality; user can check the supported ID first before performing the actual functionality.
PM_CLOCK_ENABLE 0x24 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to enable the clock.
PM_CLOCK_DISABLE 0x25 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to disable the clock.
PM_CLOCK_GETSTATE 0x26 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to read the clock state.
PM_CLOCK_SETDIVIDER 0x27 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to set the divider value of the clock.
PM_CLOCK_GETDIVIDER 0x28 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to read the clock divider.
PM_CLOCK_GETRATE 0x2A versal_2ve_2vm 1 The API is used to read the clock rate.
PM_CLOCK_SETPARENT 0x2B Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to set the parent of the clock.
PM_CLOCK_GETPARENT 0x2C Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to read the clock parent.
PM_PLL_SET_PARAM 0x30 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to set the parameter of PLL clock.
PM_PLL_GET_PARAM 0x31 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to read the parameter of PLL clock.
PM_PLL_SET_MODE 0x32 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to set the mode of PLL clock.
PM_PLL_GET_MODE 0x33 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 1 The API is used to read the mode of PLL clock.
PM_REGISTER_ACCESS 0x34 Zynq UltraScale+ MPSoC 1 The API is used for register read/write access data.
Note: Deprecated in Versal but supported in Zynq UltraScale+ MPSoC.
PM_EFUSE_ACCESS 0x35 Zynq UltraScale+ MPSoC 1 The API is used to provide access to efuse memory.
Note: Deprecated in Versal but supported in Zynq UltraScale+ MPSoC.
PM_FEATURE_CHECK 0x3F Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC 2 V1 - The API is used to return supported version of the given API.
V2 - Added support of bitmask payload functionality.

XilPM IOCTL IDs Detail

This section provides the details of the IOCTL IDs which are supported across the different platforms with brief descriptions.

Table 2. XilPM IOCTL IDs Detail
Name ID Platform Description
IOCTL_GET_RPU_OPER_MODE 0 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Get RPU mode.
IOCTL_SET_RPU_OPER_MODE 1 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Set RPU mode.
IOCTL_RPU_BOOT_ADDR_CONFIG 2 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC RPU boot address config.
IOCTL_TCM_COMB_CONFIG 3 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC TCM config.
IOCTL_SET_TAPDELAY_BYPASS 4 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC TAP delay bypass.
IOCTL_SD_DLL_RESET 6 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC SD DLL reset.
IOCTL_SET_SD_TAPDELAY 7 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC SD TAP delay.
IOCTL_SET_PLL_FRAC_MODE 8 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Set PLL frac mode.
IOCTL_GET_PLL_FRAC_MODE 9 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Get PLL frac mode.
IOCTL_SET_PLL_FRAC_DATA 10 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Set PLL frac data.
IOCTL_GET_PLL_FRAC_DATA 11 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Get PLL frac data.
IOCTL_WRITE_GGS 12 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Write GGS.
IOCTL_READ_GGS 13 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Read GGS.
IOCTL_WRITE_PGGS 14 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Write PGGS.
IOCTL_READ_PGGS 15 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Read PGGS.
IOCTL_ULPI_RESET 16 Zynq UltraScale+ MPSoC ULPI reset.
IOCTL_SET_BOOT_HEALTH_STATUS 17 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Set boot status.
IOCTL_AFI 18 Zynq UltraScale+ MPSoC AFI.
IOCTL_OSPI_MUX_SELECT 21 Versal OSPI mux select.
IOCTL_USB_SET_STATE 22 Versal USB set state.
IOCTL_GET_LAST_RESET_REASON 23 Versal Get last reset reason.
IOCTL_AIE_ISR_CLEAR 24 Versal AIE ISR clear.
IOCTL_REGISTER_SGI 25 None Register SGI to ATF.
IOCTL_SET_FEATURE_CONFIG 26 Zynq UltraScale+ MPSoC Set runtime feature config.
IOCTL_GET_FEATURE_CONFIG 27 Zynq UltraScale+ MPSoC Get runtime feature config.
IOCTL_READ_REG 28 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Read a 32-bit register.
IOCTL_MASK_WRITE_REG 29 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC RMW a 32-bit register.
IOCTL_SET_SD_CONFIG 30 Zynq UltraScale+ MPSoC Set SD config register value.
IOCTL_SET_GEM_CONFIG 31 Zynq UltraScale+ MPSoC Set GEM config register value.
IOCTL_SET_USB_CONFIG 32 Zynq UltraScale+ MPSoC Set USB config register value.
IOCTL_AIE_OPS 33 Versal adaptive SoC, Versal AI Edge Series Gen 2, and Versal Prime Series Gen 2 AIE1/AIEML Run Time Operations.
IOCTL_GET_QOS 34 Versal adaptive SoC, Versal AI Edge Series Gen 2, and Versal Prime Series Gen 2 Get Device QoS value.
IOCTL_GET_APU_OPER_MODE 35 Versal adaptive SoC, Versal AI Edge Series Gen 2, and Versal Prime Series Gen 2 Get APU operation mode.
IOCTL_SET_APU_OPER_MODE 36 Versal adaptive SoC, Versal AI Edge Series Gen 2, and Versal Prime Series Gen 2 Set APU operation mode.
IOCTL_PREPARE_DDR_SHUTDOWN 37 Versal adaptive SoC, Versal AI Edge Series Gen 2, and Versal Prime Series Gen 2 Prepare DDR for shut down.
IOCTL_GET_SSIT_TEMP 38 Versal adaptive SoC, Versal AI Edge Series Gen 2, and Versal Prime Series Gen 2 Get secondary SLR min/max temperature.
IOCTL_AIE2PS_OPS 39 Versal adaptive SoC, Versal AI Edge Series Gen 2, and Versal Prime Series Gen 2 AIE2PS Operations.
IOCTL_SET_AIE_CLK_DIV 40 Versal adaptive SoC, Versal AI Edge Series Gen 2, and Versal Prime Series Gen 2 Set AIE clock divider.

XilPM QUERY IDs Detail

This section provides the details of the QUERY IDs which are supported across the different platforms and their brief descriptions.

Table 3. XilPM QUERY IDs Detail
Name ID Platform Description
XPM_QID_INVALID 0 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Invalid Query ID.
XPM_QID_CLOCK_GET_NAME 1 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Get clock name.
XPM_QID_CLOCK_GET_TOPOLOGY 2 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Get clock topology.
XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS 3 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Get clock fixedfactor parameter.
XPM_QID_CLOCK_GET_MUXSOURCES 4 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Get clock mux sources.
XPM_QID_CLOCK_GET_ATTRIBUTES 5 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Get clock attributes.
XPM_QID_PINCTRL_GET_NUM_PINS 6 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Get total pins.
XPM_QID_PINCTRL_GET_NUM_FUNCTIONS 7 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Get total pin functions.
XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS 8 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Get total pin function groups.
XPM_QID_PINCTRL_GET_FUNCTION_NAME 9 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Get pin function name.
XPM_QID_PINCTRL_GET_FUNCTION_GROUPS 10 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Get pin function groups.
XPM_QID_PINCTRL_GET_PIN_GROUPS 11 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Get pin groups.
XPM_QID_CLOCK_GET_NUM_CLOCKS 12 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Get number of clocks.
XPM_QID_CLOCK_GET_MAX_DIVISOR 13 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Get max clock divisor.
XPM_QID_PLD_GET_PARENT 14 Versal adaptive SoC, Versal AI Edge Series Gen 2, and Versal Prime Series Gen 2, Get PLD parent.
XPM_QID_PINCTRL_GET_ATTRIBUTES 15 Versal adaptive SoC, Versal AI Edge Series Gen 2, and Versal Prime Series Gen 2, Get pin attributes.
XPM_QID_GET_NODE_NAME 16 Zynq UltraScale+ MPSoC/versal_2ve_2vm Get node name.
XPM_QID_GET_NODE_COUNT 17 Zynq UltraScale+ MPSoC/versal_2ve_2vm Get node count.

XilPM GET_OP_CHAR IDs Detail

This section provides the details of the GET_OP_CHAR IDs which are supported across the different platforms and their brief descriptions.

Table 4. XilPM GET_OP_CHAR IDs Detail
Name ID Platform Description
PM_OPCHAR_TYPE_POWER 1 Zynq UltraScale+ MPSoC Operating characteristic ID power.
PM_OPCHAR_TYPE_TEMP 2 Versal adaptive SoC, Versal AI Edge Series Gen 2, and Versal Prime Series Gen 2, Operating characteristic ID temperature.
PM_OPCHAR_TYPE_LATENCY 3 Versal adaptive SoC, Versal AI Edge Series Gen 2, Versal Prime Series Gen 2, and Zynq UltraScale+ MPSoC Operating characteristic ID latency.