This API checks if cache coherency is supported on the current processor. For Arm
AArch64 processors, coherency through CCI/CMN is allowed only at EL1 NonSecure. For
other cores such as Arm Cortex-R5, MicroBlaze, and RISC-V, coherency is not
supported.
Prototype
u32 XIOCoherencySupported(void);Parameters
The following table lists the XIOCoherencySupported function
arguments.
| Name | Description |
|---|---|
| None. |
Returns
TRUE if coherency is supported, otherwise FALSE.