The following features are not supported by the XilSEM library:
- XilSEM library does not operate on soft errors outside of the configuration RAM and NPI Registers. Soft error mitigation in other device resources, if required, based on design requirements, must be addressed at the user design level through measures such as redundancy or error detection and correction codes.
- XilSEM library initializes and manages the integrated silicon features for soft error mitigation and when included in a design, do not modify settings of associated features in the PMC.
- Design simulations that include the XilSEM library are supported. However, it is not possible to observe the library and integrated silicon features in simulation. Hardware-based evaluation is required.
- XilSEM library is not explicitly designed for use under high irradiation environments, including but not limited to the space or artificially generated environments. Therefore, AMD offers only limited guidance specific to the application of the XilSEM library in such environments.
- Debug prints are not enabled in the XilSEM library. For debug information, use
XSem_CmdCfrGetStatusandXSem_CmdNpiGetStatusfunctions. See XilSEM Library Versal adaptive SoC Client APIs for more information. The notification is through optional IPI and GPO. For more information, see Listening for SEU Detection. - XilSEM library is delivered pre-compiled as a pre-verified solution and source code is not provided. User modification of the XilSEM library is not supported.
- For Versal segmented designs:
- SW ECC for CRAM and SW SHA for NPI scan are not supported for SSI technology devices
- DFX is not supported for SW ECC and SW SHA.
- For Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 devices:
- NPI scan is supported with HW SHA only. SW SHA option is not supported.