Definition
#define Xil_EnableNestedInterrupts__asm__ __volatile__ ("stmfd sp!, {lr}"); \
__asm__ __volatile__ ("mrs lr, spsr"); \
__asm__ __volatile__ ("stmfd sp!, {lr}"); \
__asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
__asm__ __volatile__ ("stmfd sp!, {lr}");Description
Enable nested interrupts by clearing the I and F bits in CPSR.This API is defined for cortex-a9 and cortex-r5.
Note: This macro is recommended to use from interrupt handlers. In the
interrupt handler the interrupts are disabled by default (I and F are 1). Use this macro
to allow nesting of interrupts. It clears the I and F bits by changing the ARM mode to
system mode. Once these bits are cleared and the preemption of interrupt conditions are
met in the GIC, nesting of interrupts starts. Caution: This macro must be used with
caution. Before calling this macro, ensure that the source of the current IRQ is
appropriately cleared. Otherwise, as soon as I and F bits are cleared, there can be an
infinite loop of interrupts with an eventual crash (consumes all stack space).