The lwip220 supports both raw API and socket API:
- The raw API is customized for high performance and lower memory overhead. The limitation of raw API is that it is callback-based, and consequently does not provide portability to other TCP stacks.
- The socket API provides a BSD socket-style interface and is very portable; however, this mode is not as efficient as raw API mode in performance and memory requirements. The lwip220 also provides the ability to set the priority on TCP/IP and other lwIP application threads.
The following table describes the lwIP library API mode options.
| Attribute | Description | Type | Default |
|---|---|---|---|
| api_mode {RAW_API | SOCKET_API} | The lwIP library mode of operation | enum | RAW API |
| socket_mode_thread_prio | Priority of lwIP TCP/IP thread and all lwIP application threads. It is recommended that all threads using lwIP run at the same priority level. For GigE based Zynq 7000, Zynq UltraScale+ MPSoC, and Versal systems using FreeRTOS, set the appropriate priority. The default priority of 1 does not provide the expected behavior. For FreeRTOS (Zynq 7000, Zynq UltraScale+ MPSoC, and Versal adaptive SoC systems), all internal lwIP tasks (except the main TCP/IP task) are created with the priority level set for this attribute. The TCP/IP task is given a higher priority than other tasks for improved performance. The typical TCP/IP task priority is 1 more than the priority set for this attribute for FreeRTOS. | integer | 1 |
| use_axieth_on_zynq | When AxiEthernet soft IP is used on a Zynq 7000 device or a Zynq UltraScale+ MPSoC. This option ensures that the GigE on the Zynq 7000 PS (EmacPs) is not enabled and the device uses the AxiEthernet soft IP for Ethernet traffic. The existing AMD provided lwIP adapters are not tested for multiple MACs. Multiple Axi Ethernet's are not supported on Zynq UltraScale+ MPSoCs. | integer |
0 = Use Zynq 7000 PS-based or Zynq UltraScale+ MPSoC PS-based GigE controller 1= User AxiEthernet |