There are few configurable parameters available in BSP settings which are configurable during compilation of board support package in the Vitis Unified IDE. For more information on BSP configuration, see Setting Up Software System in the Vitis Unified IDE.
Configurations For Adding New device
The following configurations helps in adding new device information not supported by default.
Currently, MicroBlaze, Zynq UltraScale, and Zynq UltraScale+ MPSoC devices are
supported.
| Parameter Name | Description |
|---|---|
| device_id | Mention the device ID |
| device_irlen | Mention IR length of the device. Default is 0 |
| device_numslr | Mention number of SLRs available. Range of values can be 1 to 4. Default is 1. If no slaves are present and only one master SLR is available then only 1 number of SLR is available. |
| device_series | Select the device series. Default is FPGA SERIES ZYNQ. The following device series are supported:XSK_FPGA_SERIES_ZYNQ - Select if the device belongs to the Zynq 7000 family. XSK_FPGA_SERIES_ULTRA - Select if the device belongs to the Zynq UltraScale family. XSK_FPGA_SERIES_ULTRA_PLUS - Select if the device belongs to Zynq UltraScale MPSoC family. |
| device_masterslr | Mention the master SLR number. Default is 0. |
Configurations For Zynq UltraScale+ MPSoC devices
| Parameter Name | Description |
|---|---|
| override_sysmon_cfg | Default = TRUE, library configures sysmon before accessing efuse memory. If you are using the Sysmon library and XilSkey library together, XilSkey overwrites the user defined sysmon configuration by default. When override_sysmon_cfg is set to false, XilSkey expects you to configure the sysmon to read the 3 ADC channels - Supply 1 (VPINT), Supply 3 (VPAUX) and LPD Temperature. XilSkey validates the user defined sysmon configuration is correct before performing the eFuse operations. |
| access_secure_crit_efuse | Enables writing and reading of security critical efuses for Zynq MPSoC, type = bool, default = false |
| access_key_manage_efuse | Enables writing and reading of key management efuses for Zynq MPSoC, type = bool, default = false |
| access_user_efuse | Enables writing and reading of user efuses for Zynq MPSoC, type = bool, default = false |
| use_puf_hd_as_user_efuse | Enables APIs to use PUF Helper data efuses as user efuses, type = bool, default = false |
Note: On UltraScale and UltraScale+ devices, there can be
multiple or single SLRs and among which one can be master and the others are slaves,
where SLR 0 is not always the master SLR. Based on the master and slave SLR order, SLRs
in this library are referred with config order index. Master SLR is mentioned with
CONFIG ORDER 0, then follows the slaves config order, CONFIG ORDER 1,2, and 3 are for
slaves in order. Due to the added support for the SSI technology devices, it is
recommended to use the updated library with updated examples only for the UltraScale and
the UltraScale+ devices.