BSP Configuration Settings - BSP Configuration Settings - 2026.1 English - UG643

Standalone Library Documentation: BSP and Libraries Document Collection (UG643)
Document ID
UG643
Release Date
2026-06-23
Version
2026.1 English

Xilfpga provides the following user configuration BSP settings.

Table 1. BSP Configuration Settings for XilFPGA
Parameter Name Type Default Value Description
secure_mode bool TRUE Enables secure Bitstream loading support.
secure_readback bool FALSE Allows the secure Bitstream configuration data read back when set to TRUE. Ensure that the application environment is secure to enable this flag.
secure_environment bool FALSE Enables the secure PL configuration using the IPI. This flag is valid only for the Cortex-A53 or the Cortex-R5 processors.
debug_mode bool FALSE Enables the Debug messages in the library.
reg_readback_en Bool TRUE Enables the FPGA configuration Register Read-back support.
data_readback_en Bool TRUE Enables the FPGA configuration Data Read-back support.
get_version_info_en Bool FALSE Fetches the Xilfpga library version information
get_feature_list_en Bool FALSE Fetches the Xilfpga library supported feature list information
skip_efuse_check_en Bool FALSE Skips the eFUSE checks for PL configuration
frame_readback_en Bool FALSE Enables the FPGA CRAM frame readback support
Note:
  • In the AMD Vitis™ Unified IDE, the parameter names are prefixed with the library name. For example, XILFPGA_base_address.
  • The parameters reg_readback_en, data_readback_en, get_version_info_en, get_feature_list_en skip_efuse_check_en and skip_efuse_check_en are not available in the Vitis Unified IDE.

For more information on BSP configuration, see Setting Up Software System in the Vitis Unified IDE.