BSP and Libraries Overview
Xilinx Standard C Libraries
Xilinx Standard C Libraries
Arithmetic Operations
Input/Output Functions
Print
putnum
xil_printf
Standalone Library v9.4
Hardware Abstraction Layer API
Assert APIs and Macros
Functions
Xil_Assert
XNullHandler
Xil_AssertSetCallback
Register IO interfacing APIs
Functions
Xil_EndianSwap16
Xil_EndianSwap32
Xil_In8
Xil_In16
Xil_In32
Xil_In64
Xil_Out8
Xil_Out16
Xil_Out32
Xil_Out64
Xil_SecureOut32
Hardware Platform Information
Functions
XGetPlatform_Info
XIOCoherencySupported
Data types for Software IP Cores
Customized APIs for Memory Operations
Functions
Xil_MemCpy
Software status codes
Test Utilities for Memory and Caches
Functions
Xil_TestDCacheRange
Xil_TestDCacheAll
Xil_TestICacheRange
Xil_TestICacheAll
Xil_TestMem32
Xil_TestMem16
Xil_TestMem8
RotateLeft
RotateRight
Xil_TestIO8
Xil_TestIO16
Xil_TestIO32
Interrupt Wrapper APIs
Interrupt Wrapper APIs
Functions
XConfigInterruptCntrl
XConnectToInterruptCntrl
XDisconnectInterruptCntrl
XStartInterruptCntrl
XEnableIntrId
XDisableIntrId
XSetPriorityTriggerType
XGetPriorityTriggerType
XStopInterruptCntrl
XRegisterInterruptHandler
XSetupInterruptSystem
XGetEncodedIntrId
XTriggerSoftwareIntr
MicroBlaze Processor API Reference
MicroBlaze Processor API
Microblaze Pseudo-asm Macros and Interrupt Handling APIs
Functions
microblaze_register_handler
microblaze_register_exception_handler
MicroBlaze Exception APIs
Functions
Xil_ExceptionNullHandler
Xil_ExceptionInit
Xil_ExceptionEnable
Xil_ExceptionDisable
Xil_ExceptionRegisterHandler
Xil_ExceptionRemoveHandler
MicroBlaze Cache APIs
Functions
Xil_DCacheDisable
Xil_ICacheDisable
Definitions
#Define Xil_L1DCacheInvalidate
#Define Xil_L2CacheInvalidate
#Define Xil_L1DCacheInvalidateRange
#Define Xil_L2CacheInvalidateRange
#Define Xil_L1DCacheFlushRange
#Define Xil_L2CacheFlushRange
#Define Xil_L1DCacheFlush
#Define Xil_L2CacheFlush
#Define Xil_L1ICacheInvalidateRange
#Define Xil_L1ICacheInvalidate
#Define Xil_L1DCacheEnable
#Define Xil_L1DCacheDisable
#Define Xil_L1ICacheEnable
#Define Xil_L1ICacheDisable
#Define Xil_DCacheEnable
#Define Xil_ICacheEnable
#Define Xil_DCacheInvalidate
#Define Xil_DCacheInvalidateRange
#Define Xil_DCacheFlush
#Define Xil_DCacheFlushRange
#Define Xil_ICacheInvalidate
#Define Xil_ICacheInvalidateRange
MicroBlaze Processor FSL Macros
Definitions
#Define getfslx
#Define putfslx
#Define tgetfslx
#Define tputfslx
#Define getdfslx
#Define putdfslx
#Define tgetdfslx
#Define tputdfslx
MicroBlaze PVR access routines and macros
Functions
microblaze_get_pvr
Definitions
#Define MICROBLAZE_PVR_IS_FULL
#Define MICROBLAZE_PVR_USE_BARREL
#Define MICROBLAZE_PVR_USE_DIV
#Define MICROBLAZE_PVR_USE_HW_MUL
#Define MICROBLAZE_PVR_USE_FPU
#Define MICROBLAZE_PVR_USE_ICACHE
#Define MICROBLAZE_PVR_USE_DCACHE
Sleep Routines for MicroBlaze
Functions
Xil_SetMBFrequency
Xil_GetMBFrequency
MB_Sleep
MicroBlaze V Processor API Reference
RISC-V Processor Boot Code
MicroBlaze RISC-V Processor FSL Macros
RISC-V Pseudo-asm Macros and Interrupt Handling APIs
Functions
riscv_enable_interrupts
riscv_disable_interrupts
riscv_register_handler
Sleep Routines for RISC-V
RISC-V Cache APIs
Definitions
#Define Xil_L1DCacheInvalidate
#Define Xil_L2CacheInvalidate
#Define Xil_L1DCacheInvalidateRange
#Define Xil_L2CacheInvalidateRange
#Define Xil_L1DCacheFlushRange
#Define Xil_L2CacheFlushRange
#Define Xil_L1DCacheFlush
#Define Xil_L2CacheFlush
#Define Xil_L1ICacheInvalidateRange
#Define Xil_L1ICacheInvalidate
#Define Xil_L1DCacheEnable
#Define Xil_L1DCacheDisable
#Define Xil_L1ICacheEnable
#Define Xil_L1ICacheDisable
#Define Xil_DCacheEnable
#Define Xil_ICacheEnable
RISC-V exception APIs
Functions
Xil_ExceptionNullHandler
Xil_ExceptionInit
Xil_ExceptionEnable
Xil_ExceptionDisable
Xil_ExceptionRegisterHandler
Xil_ExceptionRemoveHandler
Processor Specific Include Files
Arm Processor Common APIs
Arm Event Counters Functions
Functions
Xpm_SetEvents
Xpm_GetEventCounters
Xpm_DisableEvent
Xpm_SetUpAnEvent
Xpm_GetEventCounter
Xpm_DisableEventCounters
Xpm_EnableEventCounters
Xpm_ResetEventCounters
Xpm_SleepPerfCounter
Arm Processor Exception Handling
Functions
Xil_ExceptionRegisterHandler
Xil_ExceptionRemoveHandler
Xil_GetExceptionRegisterHandler
Xil_ExceptionInit
Xil_DataAbortHandler
Xil_PrefetchAbortHandler
Xil_UndefinedExceptionHandler
Definitions
Define Xil_ExceptionEnableMask
Define Xil_ExceptionEnable
Define Xil_ExceptionDisableMask
Define Xil_ExceptionDisable
Define Xil_EnableNestedInterrupts
Define Xil_DisableNestedInterrupts
Arm Cortex-R5F and Cortex-R52 Processor APIs
Arm Cortex-R5F and Cortex-R52 Processor API
Arm Cortex-R5F and Cortex-R52 Processor Boot Code
Arm Cortex-R5F and Cortex-R52 Processor MPU Specific APIs
Functions
Xil_SetTlbAttributes
Xil_EnableMPU
Xil_DisableMPU
Xil_SetMPURegion
Xil_UpdateMPUConfig
Xil_GetMPUConfig
Xil_GetNumOfFreeRegions
Xil_GetNextMPURegion
Xil_DisableMPURegionByRegNum
Xil_GetMPUFreeRegMask
Xil_SetMPURegionByRegNum
Xil_MemMap
Arm Cortex-R5F and Cortex-R52 Processor Cache Functions
Functions
Xil_DCacheEnable
Xil_DCacheDisable
Xil_DCacheInvalidate
Xil_DCacheInvalidateRange
Xil_DCacheFlush
Xil_DCacheFlushRange
Xil_DCacheInvalidateLine
Xil_DCacheFlushLine
Xil_DCacheStoreLine
Xil_ICacheEnable
Xil_ICacheDisable
Xil_ICacheInvalidate
Xil_ICacheInvalidateRange
Xil_ICacheInvalidateLine
Arm Cortex-R5F and Cortex-R52 Time Functions
Functions
XTime_SetTime
XTime_GetTime
Arm Cortex-R5F and Cortex-R52 Processor Specific Include Files
Cortex R5 peripheral definitions
Arm Cortex-A9 Processor APIs
Arm Cortex-A9 Processor API
Arm Cortex-A9 Processor Boot Code
Arm Cortex-A9 Processor Cache Functions
Functions
Xil_DCacheEnable
Xil_DCacheDisable
Xil_DCacheInvalidate
Xil_DCacheInvalidateRange
Xil_DCacheFlush
Xil_DCacheFlushRange
Xil_ICacheEnable
Xil_ICacheDisable
Xil_ICacheInvalidate
Xil_ICacheInvalidateRange
Xil_DCacheInvalidateLine
Xil_DCacheFlushLine
Xil_DCacheStoreLine
Xil_ICacheInvalidateLine
Xil_L1DCacheEnable
Xil_L1DCacheDisable
Xil_L1DCacheInvalidate
Xil_L1DCacheInvalidateLine
Xil_L1DCacheInvalidateRange
Xil_L1DCacheFlush
Xil_L1DCacheFlushLine
Xil_L1DCacheFlushRange
Xil_L1DCacheStoreLine
Xil_L1ICacheEnable
Xil_L1ICacheDisable
Xil_L1ICacheInvalidate
Xil_L1ICacheInvalidateLine
Xil_L1ICacheInvalidateRange
Xil_L2CacheEnable
Xil_L2CacheDisable
Xil_L2CacheInvalidate
Xil_L2CacheInvalidateLine
Xil_L2CacheInvalidateRange
Xil_L2CacheFlush
Xil_L2CacheFlushLine
Xil_L2CacheFlushRange
Xil_L2CacheStoreLine
Arm Cortex-A9 Processor MMU Functions
Functions
Xil_SetTlbAttributes
Xil_EnableMMU
Xil_DisableMMU
Xil_MemMap
Arm Cortex-A9 Time Functions
Functions
XTime_SetTime
XTime_GetTime
PL310 L2 Event Counters Functions
Functions
XL2cc_EventCtrInit
XL2cc_EventCtrStart
XL2cc_EventCtrStop
Arm Cortex-A9 Processor and pl310 Errata Support
Definitions
Define CONFIG_ARM_ERRATA_775420
Define CONFIG_ARM_ERRATA_794073
Define CONFIG_PL310_ERRATA_588369
Define CONFIG_PL310_ERRATA_727915
Arm Cortex-A9 Processor Specific Include Files
Arm Cortex-A53 32-bit Processor APIs
Arm Cortex-A53 32-bit Processor API
Arm Cortex-A53 32-bit Processor Boot Code
Arm Cortex-A53 32-bit Processor Cache Functions
Functions
Xil_DCacheEnable
Xil_DCacheDisable
Xil_DCacheInvalidate
Xil_DCacheInvalidateRange
Xil_DCacheFlush
Xil_DCacheFlushRange
Xil_DCacheInvalidateLine
Xil_DCacheFlushLine
Xil_ICacheInvalidateLine
Xil_ICacheEnable
Xil_ICacheDisable
Xil_ICacheInvalidate
Xil_ICacheInvalidateRange
Arm Cortex-A53 32-bit Processor MMU Handling
Functions
Xil_SetTlbAttributes
Xil_EnableMMU
Xil_DisableMMU
Arm Cortex-A53 32-bit Mode Time Functions
Functions
XTime_SetTime
XTime_GetTime
Arm Cortex-A53 32-bit Processor Specific Include Files
Arm Cortex-A53, Cortex-A72, and Cortex-A78 64-bit Processor APIs
Arm Cortex-A53, Cortex-A72, and Cortex-A78 64-bit Processor API
Arm Cortex-A53, Cortex-A72, and Cortex-A78 64-bit Processor Boot Code
Arm Cortex-A53, Cortex-A72, and Cortex-A78 64-bit Processor Cache Functions
Functions
Xil_DCacheEnable
Xil_DCacheDisable
Xil_DCacheInvalidate
Xil_DCacheInvalidateRange
Xil_DCacheInvalidateLine
Xil_DCacheFlush
Xil_DCacheFlushLine
Xil_ICacheEnable
Xil_ICacheDisable
Xil_ICacheInvalidate
Xil_ICacheInvalidateRange
Xil_ICacheInvalidateLine
Xil_ConfigureL1Prefetch
Arm Cortex-A53, Cortex-A72, and Cortex-A78 64-bit Processor MMU Handling
Functions
Xil_SetTlbAttributes
Arm Cortex-A53, Cortex-A72, and Cortex-A78 64-bit Mode Time Functions
Functions
XTime_SetTime
XTime_GetTime
Arm Cortex-A53, Cortex-A72, and Cortex-A78 64-bit Processor Specific Include Files
LwIP 2.2.0 Library v1.3
Introduction
Features
Using lwIP
Overview
Setting up the Hardware System
Setting up the Software System
Configuring lwIP Options
Customizing lwIP API Mode
Configuring Xilinx Adapter Options
Configuring Memory Options
Configuring Packet Buffer (Pbuf) Memory Options
Configuring ARP Options
Configuring IP Options
Configuring ICMP Options
Configuring IGMP Options
Configuring UDP Options
Configuring TCP Options
Configuring DHCP Options
Configuring the Stats Option
Configuring the Debug Option
LwIP Library APIs
Raw API
Socket API
Using the Xilinx Adapter Helper Functions
Functions
xemacif_input_thread
xemac_add
lwip_init
xemacif_input
xemacpsif_resetrx_on_no_rxdata
XilFlash Library v4.12
Overview
Device Geometry
XilFlash Library API
Functions
XFlash_Initialize
XFlash_Reset
XFlash_DeviceControl
XFlash_Read
XFlash_Write
XFlash_Erase
XFlash_Lock
XFlash_Unlock
XFlash_IsReady
Library Parameters in MSS File in Vitis Classic IDE
Data Structures
XFlashCommandSet
XFlashPartID
XFlashProgCap
XFlashProperties
XFlashTiming
XilFFS Library v5.5
XilFFS Library API Reference
Selecting a File System
Library Parameters in MSS File in Vitis Classic IDE
XilSecure Library v5.6
Overview
AES-GCM
AES-GCM Error Codes
AES-GCM Usage to decrypt Boot Image
XilSecure AES Zynq UltraScale+ MPSoC APIs
Functions
XSecure_AesInitialize
XSecure_AesDecryptInit
XSecure_AesDecryptUpdate
XSecure_AesDecryptData
XSecure_AesDecrypt
XSecure_AesEncryptInit
XSecure_AesEncryptUpdate
XSecure_AesEncryptData
XSecure_AesReset
Definitions
XSecure_AesWaitForDone
AES-GCM API Example Usage
RSA
XilSecure RSA Zynq UltraScale+ MPSoC APIs
Functions
XSecure_RsaCfgInitialize
XSecure_RsaOperation
XSecure_RsaGetTPadding
Enumerations
Enumeration XSecure_RsaState
Definitions
XSECURE_CSU_RSA_STATUS_DONE
XSECURE_CSU_RSA_STATUS_BUSY
XSECURE_CSU_RSA_STATUS_ERROR
XSECURE_CSU_RSA_STATUS_PROG_CNT
XSECURE_CSU_RSA_CONTROL_512
XSECURE_CSU_RSA_CONTROL_576
XSECURE_CSU_RSA_CONTROL_704
XSECURE_CSU_RSA_CONTROL_768
XSECURE_CSU_RSA_CONTROL_992
XSECURE_CSU_RSA_CONTROL_1024
XSECURE_CSU_RSA_CONTROL_1152
XSECURE_CSU_RSA_CONTROL_1408
XSECURE_CSU_RSA_CONTROL_1536
XSECURE_CSU_RSA_CONTROL_1984
XSECURE_CSU_RSA_CONTROL_2048
XSECURE_CSU_RSA_CONTROL_3072
XSECURE_CSU_RSA_CONTROL_4096
XSECURE_CSU_RSA_CONTROL_DCA
XSECURE_CSU_RSA_CONTROL_NOP
XSECURE_CSU_RSA_CONTROL_EXP
XSECURE_CSU_RSA_CONTROL_EXP_PRE
XSECURE_CSU_RSA_CONTROL_MASK
XSECURE_RSA_FAILED
XSECURE_RSA_DATA_VALUE_ERROR
XSECURE_RSA_ZEROIZE_ERROR
XSECURE_HASH_TYPE_SHA3
XSECURE_FSBL_SIG_SIZE
XSECURE_RSA_MAX_BUFF
XSECURE_RSA_MAX_RD_WR_CNT
XSECURE_RSA_BYTE_MASK
XSECURE_RSA_BYTE_SHIFT
XSECURE_RSA_HWORD_SHIFT
XSECURE_RSA_SWORD_SHIFT
XSECURE_RSA_512_KEY_SIZE
XSECURE_RSA_576_KEY_SIZE
XSECURE_RSA_704_KEY_SIZE
XSECURE_RSA_768_KEY_SIZE
XSECURE_RSA_992_KEY_SIZE
XSECURE_RSA_1024_KEY_SIZE
XSECURE_RSA_1152_KEY_SIZE
XSECURE_RSA_1408_KEY_SIZE
XSECURE_RSA_1536_KEY_SIZE
XSECURE_RSA_1984_KEY_SIZE
XSECURE_RSA_2048_KEY_SIZE
XSECURE_RSA_3072_KEY_SIZE
XSECURE_RSA_4096_KEY_SIZE
XSECURE_RSA_512_SIZE_WORDS
XSECURE_RSA_576_SIZE_WORDS
XSECURE_RSA_704_SIZE_WORDS
XSECURE_RSA_768_SIZE_WORDS
XSECURE_RSA_992_SIZE_WORDS
XSECURE_RSA_1024_SIZE_WORDS
XSECURE_RSA_1152_SIZE_WORDS
XSECURE_RSA_1408_SIZE_WORDS
XSECURE_RSA_1536_SIZE_WORDS
XSECURE_RSA_1984_SIZE_WORDS
XSECURE_RSA_2048_SIZE_WORDS
XSECURE_RSA_3072_SIZE_WORDS
XSECURE_RSA_4096_SIZE_WORDS
XSECURE_CSU_RSA_RAM_EXPO
XSECURE_CSU_RSA_RAM_MOD
XSECURE_CSU_RSA_RAM_DIGEST
XSECURE_CSU_RSA_RAM_SPAD
XSECURE_CSU_RSA_RAM_RES_Y
XSECURE_CSU_RSA_RAM_RES_Q
XSECURE_RSA_SIGN_ENC
XSECURE_RSA_SIGN_DEC
XilSecure RSA Common APIs
Functions
XSecure_RsaInitialize
XSecure_RsaInitialize_64Bit
XSecure_RsaSignVerification
XSecure_RsaSignVerification_64Bit
XSecure_RsaPublicEncrypt
XSecure_RsaPublicEncrypt_64Bit
XSecure_RsaPrivateDecrypt
XSecure_RsaPrivateDecrypt_64Bit
Definitions
XSECURE_RSA_BYTE_PAD_LENGTH
XSECURE_RSA_T_PAD_LENGTH
XSECURE_RSA_BYTE_PAD1
XSECURE_RSA_BYTE_PAD2
XSECURE_RSA_BYTE_PAD3
XSECURE_RSA_INVALID_PARAM
XSECURE_RSA_STATE_MISMATCH_ERROR
RSA API Example Usage
SHA-3
XilSecure SHA3 Zynq UltraScale+ MPSoC APIs
Functions
XSecure_Sha3Initialize
XSecure_Sha3Start
XSecure_Sha3Update
XSecure_Sha3Finish
XSecure_Sha3Digest
XSecure_Sha3_ReadHash
XSecure_Sha3PadSelection
XSecure_Sha3LastUpdate
XSecure_Sha3WaitForDone
SHA-3 API Example Usage
Data Structures
XSecure_DataAddr
XSecure_RsaKey
XSecure_AesParams
XSecure_PartitionHeader
XSecure_ImageInfo
XSecure_AuthParam
XSecure_Rsa
XilSkey Library v7.8
Overview
Board Support Package Settings
Hardware Setup
BBRAM PL APIs
Functions
XilSKey_Bbram_Program
XilSKey_Bbram_JTAGServerInit
Zynq UltraScale+ MPSoC BBRAM PS API
Functions
XilSKey_ZynqMp_Bbram_Program
XilSKey_ZynqMp_Bbram_Zeroise
Zynq eFUSE PS APIs
Functions
XilSKey_EfusePs_Write
XilSKey_EfusePs_Read
XilSKey_EfusePs_ReadStatus
Zynq UltraScale+ MPSoC eFUSE PS APIs
Functions
XilSKey_ZynqMp_EfusePs_CheckAesKeyCrc
XilSKey_ZynqMp_EfusePs_ReadUserFuse
XilSKey_ZynqMp_EfusePs_ReadPpk0Hash
XilSKey_ZynqMp_EfusePs_ReadPpk1Hash
XilSKey_ZynqMp_EfusePs_ReadSpkId
XilSKey_ZynqMp_EfusePs_ReadDna
XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits
XilSKey_ZynqMp_EfusePs_CacheLoad
XilSKey_ZynqMp_EfusePs_Write
XilSkey_ZynqMpEfuseAccess
XilSKey_ZynqMp_EfusePs_SetTimerValues
XilSKey_ZynqMp_EfusePs_ReadRow
XilSKey_ZynqMp_EfusePs_SetWriteConditions
XilSKey_ZynqMp_EfusePs_WriteAndVerifyBit
XilSKey_ZynqMp_EfusePs_Init
XilSKey_ZynqMp_EfusePs_CheckForZeros
XilSKey_ZynqMp_EfusePs_ProgramPufAsUserFuses
XilSKey_ZynqMp_EfusePs_ReadPufAsUserFuses
XilSKey_ZynqMp_EfusePs_WritePufHelprData
XilSKey_ZynqMp_EfusePs_ReadPufHelprData
XilSKey_ZynqMp_EfusePs_WritePufChash
XilSKey_ZynqMp_EfusePs_ReadPufChash
XilSKey_ZynqMp_EfusePs_WritePufAux
XilSKey_ZynqMp_EfusePs_ReadPufAux
XilSKey_Write_Puf_EfusePs_SecureBits
XilSKey_Read_Puf_EfusePs_SecureBits
XilSKey_Puf_Registration
XilSKey_Puf_Regeneration
eFUSE PL APIs
Functions
XilSKey_EfusePl_SystemInit
XilSKey_EfusePl_Program
XilSKey_EfusePl_ReadStatus
XilSKey_EfusePl_ReadKey
CRC Calculation API
Functions
XilSKey_CrcCalculation
XilSkey_CrcCalculation_AesKey
User-Configurable Parameters
Zynq User-Configurable PS eFUSE Parameters
Zynq User-Configurable PL eFUSE Parameters
MIO Pins for Zynq PL eFUSE JTAG Operations
MUX Selection Pin for Zynq PL eFUSE JTAG Operations
MUX Parameter for Zynq PL eFUSE JTAG Operations
AES and User Key Parameters
Zynq User-Configurable PL BBRAM Parameters
MUX Parameter for Zynq BBRAM PL JTAG Operations
AES and User Key Parameters
UltraScale or UltraScale+ User-Configurable BBRAM PL Parameters
AES and User Key Parameters
DPA Protection for BBRAM Key
GPIO Device Used for Connecting PL Master JTAG Signals
GPIO Pins Used for PL Master JTAG Signals
GPIO Channels
UltraScale or UltraScale+ User-Configurable PL eFUSE Parameters
GPIO Device Used for Connecting PL Master JTAG Signals
GPIO Pins Used for PL Master JTAG and HWM Signals
GPIO Channels
SLR Selection to Program eFUSE on Monolithic/SSI Technology Devices
eFUSE PL Read Parameters
AES Keys and Related Parameters
User Keys (32-bit) and Related Parameters
RSA Hash and Related Parameters
User Keys (128-bit) and Related Parameters
AES Key CRC verification
Zynq UltraScale+ MPSoC User-Configurable PS eFUSE Parameters
AES Keys and Related Parameters
User Keys and Related Parameters
PPK0 Keys and Related Parameters
PPK1 Keys and Related Parameters
SPK ID and Related Parameters
Zynq UltraScale+ MPSoC User-Configurable PS BBRAM Parameters
Zynq UltraScale+ MPSoC User-Configurable PS PUF Parameters
Error Codes
PL EFUSE error codes
Enumerations
Enumeration XSKEfusePl_ErrorCodes
PS EFUSE error codes
Enumerations
Enumeration XSKEfusePs_ErrorCodes
Zynq UltraScale+ MPSoC BBRAM PS Error Codes
Enumerations
Enumeration XskZynqMp_Ps_Bbram_ErrorCodes
Status Codes
Procedure
Data Structures
XilSKey_EPl
XilSKey_JtagSlr
XilSKey_UsrFuses
XilPM Library v6.1
Overview
XilPM Zynq UltraScale+ MPSoC APIs
Functions
XPm_InitXilpm
XPm_GetBootStatus
XPm_SuspendFinalize
XPm_SelfSuspend
XPm_SetConfiguration
XPm_InitFinalize
XPm_RequestSuspend
XPm_RequestWakeUp
XPm_ForcePowerDown
XPm_AbortSuspend
XPm_SetWakeUpSource
XPm_SystemShutdown
XPm_RequestNode
XPm_SetRequirement
XPm_ReleaseNode
XPm_SetMaxLatency
XPm_FeatureCheck
XPm_IsFunctionSupported
XPm_InitSuspendCb
XPm_AcknowledgeCb
XPm_NotifyCb
XPm_GetApiVersion
XPm_GetNodeStatus
XPm_GetOpCharacteristic
XPm_ResetAssert
XPm_ResetGetStatus
XPm_RegisterNotifier
XPm_UnregisterNotifier
XPm_MmioWrite
XPm_MmioRead
XPm_ClockEnable
XPm_ClockDisable
XPm_ClockGetStatus
XPm_ClockSetDivider
XPm_ClockGetDivider
XPm_ClockSetParent
XPm_ClockGetParent
XPm_PllSetParameter
XPm_PllGetParameter
XPm_PllSetMode
XPm_PllGetMode
XPm_PinCtrlRequest
XPm_PinCtrlRelease
XPm_PinCtrlSetFunction
XPm_PinCtrlGetFunction
XPm_PinCtrlSetParameter
XPm_PinCtrlGetParameter
XPm_DevIoctl
Enumerations
Enumeration XPmApiCbId
Enumeration XPmNodeId
Enumeration XPmRequestAck
Enumeration XPmAbortReason
Enumeration XPmSuspendReason
Enumeration XPmRamState
Enumeration XPmBootStatus
Enumeration XPmResetAction
Enumeration XPmReset
Enumeration XPmNotifyEvent
Enumeration XPmClock
Enumeration XPmPllParam
Enumeration XPmPllMode
Enumeration XPmPinFn
Enumeration XPmPinParam
Enumeration pm_feature_id
Enumeration XPm_SdConfigType
Enumeration XPm_GemConfigType
Enumeration XPm_UsbConfigType
Definitions
Define PM_VERSION_MAJOR
Define PM_VERSION_MINOR
Define PM_VERSION
Define PM_API_BASE_VERSION
Define PM_API_VERSION_2
Define PM_CAP_ACCESS
Define PM_CAP_CONTEXT
Define PM_CAP_WAKEUP
Define NODE_STATE_OFF
Define NODE_STATE_ON
Define PROC_STATE_FORCEDOFF
Define PROC_STATE_ACTIVE
Define PROC_STATE_SLEEP
Define PROC_STATE_SUSPENDING
Define MAX_LATENCY
Define MAX_QOS
Define PMF_SHUTDOWN_TYPE_SHUTDOWN
Define PMF_SHUTDOWN_TYPE_RESET
Define PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM
Define PMF_SHUTDOWN_SUBTYPE_PS_ONLY
Define PMF_SHUTDOWN_SUBTYPE_SYSTEM
XilPM Versal Adaptive SoC APIs
Functions
XPm_InitXilpm
XPm_GetBootStatus
XPm_GetChipID
XPm_GetApiVersion
XPm_RequestNode
XPm_ReleaseNode
XPm_SetRequirement
XPm_GetNodeStatus
XPm_ResetAssert
XPm_ResetGetStatus
XPm_PinCtrlRequest
XPm_PinCtrlRelease
XPm_PinCtrlSetFunction
XPm_PinCtrlGetFunction
XPm_PinCtrlSetParameter
XPm_PinCtrlGetParameter
XPm_DevIoctl
XPm_DevIoctl2
XPm_ClockEnable
XPm_ClockDisable
XPm_ClockGetStatus
XPm_ClockSetDivider
XPm_ClockGetDivider
XPm_ClockSetParent
XPm_ClockGetParent
XPm_PllSetParameter
XPm_PllGetParameter
XPm_PllSetMode
XPm_PllGetMode
XPm_SelfSuspend
XPm_RequestWakeUp
XPm_SuspendFinalize
XPm_AbortSuspend
XPm_ForcePowerDown
XPm_SystemShutdown
XPm_SetWakeUpSource
XPm_Query
XPm_SetMaxLatency
XPm_GetOpCharacteristic
XPm_InitFinalize
XPm_RegisterNotifier
XPm_UnregisterNotifier
XPm_InitSuspendCb
XPm_AcknowledgeCb
XPm_NotifyCb
XPm_FeatureCheck
Enumerations
Enumeration XPmAbortReason
Enumeration XPmBootStatus
Enumeration XPmRequestAck
Enumeration XPmCapability
Enumeration XPmDeviceUsage
Enumeration XPmResetActions
Enumeration XPmSuspendReason
Enumeration XPmApiCbId_t
Enumeration PmPinFunIds
Enumeration pm_pinctrl_config_param
Enumeration pm_pinctrl_slew_rate
Enumeration pm_pinctrl_bias_status
Enumeration pm_pinctrl_pull_ctrl
Enumeration pm_pinctrl_schmitt_cmos
Enumeration pm_pinctrl_drive_strength
Enumeration pm_pinctrl_tri_state
Enumeration XPm_PllConfigParams
Enumeration XPmPllMode
Enumeration XPmInitFunctions
Enumeration XPmNotifyEvent
Definitions
Define PM_VERSION_MAJOR
Define PM_VERSION_MINOR
Define PM_VERSION
Define ABORT_REASON_MIN
Define ABORT_REASON_MAX
Define XPM_MAX_CAPABILITY
Define XPM_MAX_LATENCY
Define XPM_MAX_QOS
Define XPM_MIN_CAPABILITY
Define XPM_MIN_LATENCY
Define XPM_MIN_QOS
Define XPM_DEF_CAPABILITY
Define XPM_DEF_LATENCY
Define XPM_DEF_QOS
Define NODE_STATE_OFF
Define NODE_STATE_ON
Define PROC_STATE_SLEEP
Define PROC_STATE_ACTIVE
Define PROC_STATE_FORCEDOFF
Define PROC_STATE_SUSPENDING
Define PM_SHUTDOWN_TYPE_SHUTDOWN
Define PM_SHUTDOWN_TYPE_RESET
Define PM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM
Define PM_SHUTDOWN_SUBTYPE_RST_PS_ONLY
Define PM_SHUTDOWN_SUBTYPE_RST_SYSTEM
Define PM_SUSPEND_STATE_CPU_IDLE
Define PM_SUSPEND_STATE_CPU_OFF
Define PM_SUSPEND_STATE_SUSPEND_TO_RAM
Define XPM_RPU_MODE_LOCKSTEP
Define XPM_RPU_MODE_SPLIT
Define XPM_RPU_BOOTMEM_LOVEC
Define XPM_RPU_BOOTMEM_HIVEC
Define XPM_RPU_TCM_SPLIT
Define XPM_RPU_TCM_COMB
Define XPM_BOOT_HEALTH_STATUS_MASK
Define XPM_TAPDELAY_QSPI
Define XPM_TAPDELAY_BYPASS_DISABLE
Define XPM_TAPDELAY_BYPASS_ENABLE
Define XPM_OSPI_MUX_SEL_DMA
Define XPM_OSPI_MUX_SEL_LINEAR
Define XPM_OSPI_MUX_GET_MODE
Define XPM_TAPDELAY_INPUT
Define XPM_TAPDELAY_OUTPUT
Define XPM_DLL_RESET_ASSERT
Define XPM_DLL_RESET_RELEASE
Define XPM_DLL_RESET_PULSE
Define XPM_RESET_REASON_EXT_POR
Define XPM_RESET_REASON_SW_POR
Define XPM_RESET_REASON_SLR_POR
Define XPM_RESET_REASON_ERR_POR
Define XPM_RESET_REASON_DAP_SRST
Define XPM_RESET_REASON_ERR_SRST
Define XPM_RESET_REASON_SW_SRST
Define XPM_RESET_REASON_SLR_SRST
Define XPM_RESET_REASON_INVALID
Define XST_API_BASE_VERSION
Define XST_API_QUERY_DATA_VERSION
Define XST_API_REG_NOTIFIER_VERSION
Define XST_API_PM_IOCTL_VERSION
Define XST_API_PM_FEATURE_CHECK_VERSION
Define XST_API_SELF_SUSPEND_VERSION
Define XST_API_FORCE_POWERDOWN_VERSION
Define XST_API_REQUEST_NODE_VERSION
Define XST_API_RELEASE_NODE_VERSION
Define XST_API_GET_OP_CHAR_VERSION
Define AIE_OPS_COL_RST
Define AIE_OPS_SHIM_RST
Define AIE_OPS_ENB_COL_CLK_BUFF
Define AIE_OPS_ALL_MEM_ZEROIZATION
Define AIE_OPS_DIS_COL_CLK_BUFF
Define AIE_OPS_ENB_AXI_MM_ERR_EVENT
Define AIE_OPS_SET_L2_CTRL_NPI_INTR
Define AIE_OPS_PROG_MEM_ZEROIZATION
Define AIE_OPS_DATA_MEM_ZEROIZATION
Define AIE_OPS_MEM_TILE_ZEROIZATION
Define AIE_OPS_MAX
XilPM API Version Detail
Error Status
Definitions
Define XST_PM_INTERNAL
Define XST_PM_CONFLICT
Define XST_PM_NO_ACCESS
Define XST_PM_INVALID_NODE
Define XST_PM_DOUBLE_REQ
Define XST_PM_ABORT_SUSPEND
Define XST_PM_TIMEOUT
Define XST_PM_NODE_USED
Library Parameters in MSS File
Data Structure Index
pm_acknowledge
pm_init_suspend
XPm_DeviceStatus
XPm_NodeStatus
XPm_Notifier
XilPM Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 Library v1.1
Overview
XilPM Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 APIs
Functions
XPm_IpiSend
Xpm_IpiReadBuff32
XPm_GetRegisterNotifierVersionServer
XPm_InitXilpm
XPm_GetBootStatus
XPm_GetChipID
XPm_GetApiVersion
XPm_RequestNode
XPm_ReleaseNode
XPm_SetRequirement
XPm_GetNodeStatus
XPm_ResetAssert
XPm_ResetGetStatus
XPm_PinCtrlRequest
XPm_PinCtrlRelease
XPm_PinCtrlSetFunction
XPm_PinCtrlGetFunction
XPm_PinCtrlSetParameter
XPm_PinCtrlGetParameter
XPm_DevIoctl
XPm_DevIoctl2
XPm_ClockEnable
XPm_ClockDisable
XPm_ClockGetStatus
XPm_ClockSetDivider
XPm_ClockGetDivider
XPm_ClockSetParent
XPm_ClockGetParent
XPm_PllSetParameter
XPm_PllGetParameter
XPm_PllSetMode
XPm_PllGetMode
XPm_SelfSuspend
XPm_RequestWakeUp
XPm_SuspendFinalize
XPm_AbortSuspend
XPm_ForcePowerDown
XPm_SystemShutdown
XPm_SetWakeUpSource
XPm_Query
XPm_SetMaxLatency
XPm_GetOpCharacteristic
XPm_RegisterNotifier
XPm_UnregisterNotifier
XPm_InitSuspendCb
XPm_AcknowledgeCb
XPm_NotifyCb
XPm_FeatureCheck
XPm_NotifierAdd
XPm_NotifierRemove
XPm_NotifierProcessEvent
XPm_RMW32
XPm_SetPrimaryProc
XPm_GetProcByDeviceId
XPm_ClientSuspend
XPm_ClientWakeUp
XPm_ClientSuspendFinalize
XPm_ClientAbortSuspend
Enumerations
Enumeration XPmAbortReason
Enumeration XPmBootStatus
Enumeration XPmRequestAck
Enumeration XPmCapability
Enumeration XPmDeviceUsage
Enumeration XPmResetActions
Enumeration XPmSuspendReason
Enumeration XPmApiCbId_t
Enumeration pm_query_id
Enumeration PmPinFunIds
Enumeration pm_pinctrl_config_param
Enumeration pm_pinctrl_slew_rate
Enumeration pm_pinctrl_bias_status
Enumeration pm_pinctrl_pull_ctrl
Enumeration pm_pinctrl_schmitt_cmos
Enumeration pm_pinctrl_drive_strength
Enumeration pm_pinctrl_tri_state
Enumeration XPmInitFunctions
Enumeration pm_ioctl_id
Enumeration XPm_PllConfigParams
Enumeration XPmPllMode
Enumeration XPmOpCharType
Enumeration XPmNotifyEvent
Definitions
Define PM_VERSION_MAJOR
Define PM_VERSION_MINOR
Define PM_VERSION
Define ABORT_REASON_MIN
Define ABORT_REASON_MAX
Define XPM_MAX_CAPABILITY
Define XPM_MAX_LATENCY
Define XPM_MAX_QOS
Define XPM_MIN_CAPABILITY
Define XPM_MIN_LATENCY
Define XPM_MIN_QOS
Define XPM_DEF_CAPABILITY
Define XPM_DEF_LATENCY
Define XPM_DEF_QOS
Define NODE_STATE_OFF
Define NODE_STATE_ON
Define PROC_STATE_SLEEP
Define PROC_STATE_ACTIVE
Define PROC_STATE_FORCEDOFF
Define PROC_STATE_SUSPENDING
Define PM_SHUTDOWN_TYPE_SHUTDOWN
Define PM_SHUTDOWN_TYPE_RESET
Define PM_SHUTDOWN_SUBTYPE_RST_SUBSYSTEM
Define PM_SHUTDOWN_SUBTYPE_RST_PS_ONLY
Define PM_SHUTDOWN_SUBTYPE_RST_SYSTEM
Define PM_SUSPEND_STATE_CPU_IDLE
Define PM_SUSPEND_STATE_CPU_OFF
Define PM_SUSPEND_STATE_SUSPEND_TO_RAM
Define XPM_RPU_MODE_LOCKSTEP
Define XPM_RPU_MODE_SPLIT
Define XPM_APU_MODE_LOCKSTEP
Define XPM_APU_MODE_SPLIT
Define XPM_RPU_BOOTMEM_LOVEC
Define XPM_RPU_BOOTMEM_HIVEC
Define XPM_RPU_TCM_SPLIT
Define XPM_RPU_TCM_COMB
Define XPM_BOOT_HEALTH_STATUS_MASK
Define XPM_TAPDELAY_QSPI
Define XPM_TAPDELAY_BYPASS_DISABLE
Define XPM_TAPDELAY_BYPASS_ENABLE
Define XPM_OSPI_MUX_SEL_DMA
Define XPM_OSPI_MUX_SEL_LINEAR
Define XPM_OSPI_MUX_GET_MODE
Define XPM_TAPDELAY_INPUT
Define XPM_TAPDELAY_OUTPUT
Define XPM_DLL_RESET_ASSERT
Define XPM_DLL_RESET_RELEASE
Define XPM_DLL_RESET_PULSE
Define XPM_RESET_REASON_EXT_POR
Define XPM_RESET_REASON_SW_POR
Define XPM_RESET_REASON_SLR_POR
Define XPM_RESET_REASON_ERR_POR
Define XPM_RESET_REASON_DAP_SRST
Define XPM_RESET_REASON_ERR_SRST
Define XPM_RESET_REASON_SW_SRST
Define XPM_RESET_REASON_SLR_SRST
Define XPM_RESET_REASON_INVALID
Define XST_API_BASE_VERSION
Define XST_API_QUERY_DATA_VERSION
Define XST_API_REG_NOTIFIER_VERSION
Define XST_API_PM_IOCTL_VERSION
Define XST_API_PM_FEATURE_CHECK_VERSION
Define XST_API_SELF_SUSPEND_VERSION
Define XST_API_FORCE_POWERDOWN_VERSION
Define XST_API_REQUEST_NODE_VERSION
Define XST_API_RELEASE_NODE_VERSION
Define XST_API_GET_OP_CHAR_VERSION
Define XPM_DSTN_CLUSTER_0
Define XPM_DSTN_CLUSTER_1
Define XPM_DSTN_CLUSTER_2
Define XPM_DSTN_CLUSTER_3
Define XPM_DSTN_CORE_0
Define XPM_DSTN_CORE_1
Define XPM_DSTN_CORE_2
Define XPM_DSTN_CORE_3
Define GET_APU_CLUSTER_ID
Define GET_CORE
Define GET_APU_CORE_NUM
Define GET_RPU_CLUSTER_ID
Define GET_RPU_CORE_NUM
Define PACK_PAYLOAD
Define XILPM_MODULE_ID
Define HEADER
Define PACK_PAYLOAD0
Define PACK_PAYLOAD1
Define PACK_PAYLOAD2
Define PACK_PAYLOAD3
Define PACK_PAYLOAD4
Define PACK_PAYLOAD5
Define NODE_CLASS_SHIFT
Define NODE_CLASS_MASK_BITS
Define NODE_CLASS_MASK
Define NODECLASS
Define XPM_NODECLASS_EVENT
Define XPM_ARRAY_SIZE
Define MPIDR_AFFLVL_MASK
Define WFI
Define PAYLOAD_ARG_CNT
Define RESPONSE_ARG_CNT
Define PM_IPI_TIMEOUT
Define TARGET_IPI_INT_MASK
Define XPM_FALSE_COND
Define XPm_Read
Define XPm_Write
Define XpmEnableInterrupts
Define XpmDisableInterrupts
Define XPm_Dbg
Define XPm_Err
Define pm_print
Define pm_dbg
Define pm_read
Define pm_write
XilPM Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 API Version Detail
Error Status
Data Structures
pm_acknowledge
pm_init_suspend
XPm_DeviceStatus
XPm_NdStatus
XPm_Ntfier
XPm_Proc
XilFPGA Library v6.9
Overview
Supported Features
Zynq UltraScale+ MPSoC XilFPGA Library
XilFPGA library Interface modules
Design Summary
Flow Diagram
BSP Configuration Settings
Setting up the Software System
Enabling Security
Bitstream Authentication Using External Memory
Bootgen
Loading an Authenticated and Encrypted Bitstream using OCM
Loading an Authenticated and Encrypted Bitstreamusing DDR Memory Controller
Versal Adaptive SoC XilFPGA Library
Design Summary
BSP Configuration Settings
XilFPGA APIs
XilFPGA APIs for Versal Adaptive SoC and Zynq UltraScale+ MPSoC
Functions
XFpga_Initialize
XFpga_GetFeatureList
XFpga_GetVersion
XFpga_ValidateImage
XFpga_BitStream_Load
XFpga_PL_Preconfig
XFpga_Write_Pl
XFpga_PL_PostConfig
XilFPGA APIs for Zynq UltraScale+ MPSoC
Functions
XFpga_GetPlConfigData
XFpga_GetPlConfigReg
XFpga_InterfaceStatus
XilMailbox Library v1.12
Overview
Functions
XMailbox_Send
XMailbox_SendData
XMailbox_Recv
XMailbox_SetCallBack
XMailbox_SetSharedMem
XMailbox_GetSharedMem
XMailbox_ReleaseSharedMem
XMailbox_Initialize
Enumerations
Enumeration XMailbox_IpiSharedMemState
Enumeration XMailbox_Handler
XilMailbox SDT APIs
XMailbox_Initialize
Data Structure Index
XMailbox
XMailbox_IpiSharedMem
Limitations
XilSEM Library v1.12
Overview
XilSEM Features
Unsupported Features
Tool Configuration for XilSEM
Documentation
Example Usage
Initializing the SEU Mitigation
Listening for SEU Detection
Injecting Errors for Test
Injecting an Error in Configuration RAM
Injecting an Error in NPI Registers
XilSEM Operation During Partial Bitstream Loading
Specifications
Standards
Performance
Reliability
Throughput
Power
XilSEM Library Solution Reliability
XilSEM Library Versal Adaptive SoC Client APIs
Functions
XSem_CopyCmdResponse
XSem_RegisterEvent
XSem_CmdCfrInit
XSem_CmdCfrStartScan
XSem_CmdCfrStopScan
XSem_CmdCfrNjctErr
XSem_CmdCfrGetStatus
XSem_CmdCfrReadFrameEcc
XSem_CmdNpiStartScan
XSem_CmdNpiStopScan
XSem_CmdNpiInjectError
XSem_CmdNpiGetGldnSha
XSem_CmdNpiGetStatus
XSem_CmdGetConfig
XSem_CmdCfrGetCrc
XSem_CmdCfrGetTotalFrames
Data Structures
XSem_DescriptorData
XSem_DescriptorInfo
XSem_Notifier
XSem_XmpuCfg
XSemCfrErrInjData
XSemCfrStatus
XSemIpiResp
XSemNpiStatus
XSemStatus
XilTimer Library v2.3
Overview
BSP Configuration Settings
XilTimer APIs
Functions
sleep
msleep
usleep
XTimer_ReleaseTickTimer
XTimer_SetInterval
XTimer_ClearTickInterrupt
XilSleepTimer_Init
XilTickTimer_Init
XTime_GetTime
Data Structures
XTimerTag
Limitations
XilSFL Library v1.2
Overview
XilSFL Library APIs
Functions
XSfl_FlashInit
XSfl_FlashErase
XSfl_FlashWrite
XSfl_FlashReadStart
XSfl_FlashReadDone
XSfl_FlashGetInfo
XSfl_FlashRead
XSfl_OspiInit
XSfl_FlashIdRead
XSfl_CalculateFCTIndex
XSfl_FlashSetSDRDDRMode
XSfl_FlashEnterExit4BAddMode
XSfl_GetRealAddr
XSfl_SectorErase
XSfl_FlashPageWrite
XSfl_FlashReadProcess
XSfl_FlashTransferDone
XSfl_WaitforStatusDone
XSfl_FlashRegisterReadWrite
XSfl_FlashCmdTransfer
XSfl_FlashNonBlockingReadProcess
Definitions
Define XILSFL_CONTROL_H
Define XSFL_COMMAND_OFFSET
Define XSFL_ADDRESS_OFFSET
Define XSFL_ADDRESS_SIZE_OFFSET
Define XSFL_DUMMY_OFFSET
Define XSFL_FLASH_DUMMY_CYCLES_0
Define XSFL_FLASH_DUMMY_CYCLES_8
Define XSFL_FLASH_DUMMY_CYCLES_16
Define XSFL_FLASH_DUMMY_CYCLES_20
Define XSFL_FLASH_DUMMY_CYCLES_21
Define XSFL_FLASH_FREQUENCY_166_MHZ
Define XSFL_FLASH_FREQUENCY_150_MHZ
Define XSFL_BUFFER_ARRAY_LEN
Data Structures
XSfl_UserConfig::Ospi_Conig
XSfl
XSfl_CntrlInfo
XSfl_FlashInfo
XSfl_Interface
XSfl_Msg
Setting Up Software System in the Vitis Unified IDE
Adding a Library to an Existing BSP Using Vitis Unified IDE
Adding a Library to an Existing BSP Using Vitis Classic IDE
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
Revision History
References
Please Read: Important Legal Notices