TLBI Does Not Treat Upper ASID Bits As Zero When TCR_EL1.AS Is 0

Versal HBM Series Production Errata (EN334)

Document ID
EN334
Release Date
2024-02-01
Revision
1.0 English

AMD Answer 73153

TLBI instructions are not treating ASID[15:8] as zero when TCR_EL1.AS=0, as specified in the Arm Architecture Reference Manual. In this configuration, the bits are RES0, which should be written to zero by software, and ignored by hardware.

This is a third-party errata (Arm, Inc. 1406396); this issue will not be fixed.