Self-Modifying Code In Non-Cacheable Memory Might Not Work With A Slow Memory System

Versal HBM Series Production Errata (EN334)

Document ID
EN334
Release Date
2024-02-01
Revision
1.0 English

AMD Answer 73139

If a program executing on a processor writes to a non-cacheable memory location that subsequently executes an instruction from, it must issue DSB and ISB to ensure that the updated instruction is executed. Because of this errata, this sequence might not be sufficient to prevent the processor executing the old instruction or a corrupted instruction.

This is a third-party errata (Arm, Inc. 853474); this issue will not be fixed.