In RC Mode With SMMU Enabled, CCI Transaction Ordering Is Not Followed Between Different Shareability Domain Memories That Have Same AXI ID

Versal HBM Series Production Errata (EN334)

Document ID
EN334
Release Date
2024-02-01
Revision
1.0 English

AMD Answer 000034220

With the CPM as root complex (RC) and SMMU enabled, cache coherent interconnect (CCI) transaction ordering is not being followed between different shareable domain memories that have same AXI ID.

This issue will not be fixed.