ELR Recorded Incorrectly On Interrupt Taken Between Cryptographic Instructions In A Sequence

Versal HBM Series Production Errata (EN334)

Document ID
EN334
Release Date
2024-02-01
Revision
1.0 English

AMD Answer 73134

In aarch32 mode, if the code executed contains the sequence of cryptographic instructions: AESE Qy, Qx AESMC Qy, Qy or AESD Qy, Qx AESIMC Qy, Qy and an interrupt is asserted and taken just after execution of the first cryptographic instruction, then the ELR recorded as the return address might be incorrect leading to data corruption.

This is a third-party errata (Arm, Inc. 1655431); this issue will not be fixed.