See the Zynq UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG1075) for further pin descriptions.
| Pin Number | Pin Type | Signal Name | Signal Description |
|---|---|---|---|
| Connector Row A | |||
| A1 | VCC_BATT | PS BBRAM and real-time clock (RTC) supply voltage, requires external battery. Connect to GND when battery is not used. | |
| A2 | GND | Ground, connect to carrier card ground plane | |
| A3 | HPA06P | HPIO on bank 65 | |
| A4 | HPA06N | HPIO on bank 65 | |
| A5 | GND | Ground, connect to carrier card ground plane | |
| A6 | GC | HPA_CLK0P_CLK | HPIO global clock pin on bank 65 |
| A7 | GC | HPA_CLK0N | HPIO global clock pin on bank 65 |
| A8 | GND | Ground, connect to carrier card ground plane | |
| A9 | HPA12P_CLK | HPIO on bank 65 | |
| A10 | HPA12N | HPIO on bank 65 | |
| A11 | GND | Ground, connect to carrier card ground plane | |
| A12 | QBC | HPA13P | HPIO on bank 65 |
| A13 | QBC | HPA13N | HPIO on bank 65 |
| A14 | GND | Ground, connect to carrier card ground plane | |
| A15 | HDGC | HDA09 | HDIO on bank 26 |
| A16 | HDA10 | HDIO on bank 26 | |
| A17 | HDA11 | HDIO on bank 26 | |
| A18 | GND | Ground, connect to carrier card ground plane | |
| A19 | PD50 | VCCOEN_PS_M2C | Indication to turn on power for PS I/O peripherals on the carrier card |
| A20 | PD50 | VCCOEN_PL_M2C | Indication to turn on power for PL /IO peripherals on the carrier card |
| A21 | GND | Ground, connect to carrier card ground plane | |
| A22 | PU18_4p7 | JTAG_TMS_C2M | JTAG mode select |
| A23 | PU18_4p7 | JTAG_TDO_M2C | JTAG data out |
| A24 | PU18_4p7 | JTAG_TDI_C2M | JTAG data in |
| A25 | PU18_4p7 | JTAG_TCK_C2M | JTAG clock |
| A26 | GND | Ground, connect to carrier card ground plane | |
| A27 | PU18_4p7 | MODE0_C2M | PS mode bit 0 |
| A28 | PU18_4p7 | MODE1_C2M | PS mode bit 1 |
| A29 | PU18_4p7 | MODE2_C2M | PS mode bit 2 |
| A30 | PU18_4p7 | MODE3_C2M | PS mode bit 3 |
| A31 | Reserved | No connect on the SOM | |
| A32 | Reserved | No connect on the SOM | |
| A33 | GND | Ground, connect to carrier card ground plane | |
| A34 | MIO41 | PS MIO signal on bank 501 | |
| A35 | MIO42 | PS MIO signal on bank 501 | |
| A36 | MIO43 | PS MIO signal on bank 501 | |
| A37 | GND | Ground, connect to carrier card ground plane | |
| A38 | MIO61 | PS MIO signal on bank 502 | |
| A39 | MIO62 | PS MIO signal on bank 502 | |
| A40 | MIO63 | PS MIO signal on bank 502 | |
| A41 | GND | Ground, connect to carrier card ground plane | |
| A42 | MIO73 | PS MIO signal on bank 502 | |
| A43 | MIO74 | PS MIO signal on bank 502 | |
| A44 | MIO75 | PS MIO signal on bank 502 | |
| A45 | GND | Ground, connect to carrier card ground plane | |
| A46 | GND | Ground, connect to carrier card ground plane | |
| A47 | GTR_DP1_M2C_P | PS-GTR lane 1 TX, bank 505 | |
| A48 | GTR_DP1_M2C_N | PS-GTR lane 1 TX, bank 505 | |
| A49 | GND | Ground, connect to carrier card ground plane | |
| A50 | GND | Ground, connect to carrier card ground plane | |
| A51 | AC01UF | GTR_REFCLK3_C2M_P | PS-GTR REFCLK3 input, bank 505 |
| A52 | AC01UF | GTR_REFCLK3_C2M_N | PS-GTR REFCLK3 input, bank 505 |
| A53 | GND | Ground, connect to carrier card ground plane | |
| A54 | GND | Ground, connect to carrier card ground plane | |
| A55 | GTR_DP0_C2M_P | PS-GTR lane 0 RX, bank 505 | |
| A56 | GTR_DP0_C2M_N | PS-GTR lane 0 RX, bank 505 | |
| A57 | GND | Ground, connect to carrier card ground plane | |
| A58 | GND | Ground, connect to carrier card ground plane | |
| A59 | VCC_SOM | SOM main supply voltage, +5V | |
| A60 | VCC_SOM | SOM main supply voltage, +5V | |
| Connector Row B | |||
| B1 | QBC | HPA05_CCP | HPIO clock-capable pin on bank 65 |
| B2 | QBC | HPA05_CCN | HPIO clock-capable pin on bank 65 |
| B3 | GND | Ground, connect to carrier card ground plane | |
| B4 | HPA04P | HPIO on bank 65 | |
| B5 | HPA04N | HPIO on bank 65 | |
| B6 | GND | Ground, connect to carrier card ground plane | |
| B7 | HPA07P_CLK | HPIO on bank 65 | |
| B8 | HPA07N | HPIO on bank 65 | |
| B9 | GND | Ground, connect to carrier card ground plane | |
| B10 | GC | HPA11P_CLK | HPIO on bank 65 |
| B11 | GC | HPA11N | HPIO on bank 65 |
| B12 | GND | Ground, connect to carrier card ground plane | |
| B13 | VCCO_HDA | HDA I/O voltage rail, 1.2V to 3.3V | |
| B14 | VCCO_HDA | HDA I/O voltage rail, 1.2V to 3.3V | |
| B15 | GND | Ground, connect to carrier card ground plane | |
| B16 | HDA03 | HDIO on bank 26 | |
| B17 | HDA04 | HDIO on bank 26 | |
| B18 | HDA05 | HDIO on bank 26 | |
| B19 | GND | Ground, connect to carrier card ground plane | |
| B20 | HDA15 | HDIO on bank 26 | |
| B21 | HDGC | HDA16_CC | HDIO clock-capable pin on bank 26 |
| B22 | HDGC | HDA17 | HDIO on bank 26 |
| B23 | GND | Ground, connect to carrier card ground plane | |
| B24 | PS_ERROR_OUT_M2C | PS error indication from SOM | |
| B25 | PS_ERROR_STATUS_M2C | PS error status from SOM | |
| B26 | PU50 | PWROFF_C2M_B | Control signal to turn off all power rails on the SOM |
| B27 | GND | Ground, connect to carrier card ground plane | |
| B28 | MIO35 | PS MIO signal on bank 501. Optional use as PMU output. | |
| B29 | MIO36 | PS MIO signal on bank 501. Optional use as PMU output. Default use as UART TXD in the released Kria PetaLinux BSPs. | |
| B30 | MIO37 | PS MIO signal on bank 501. Optional use as PMU output. Default use as UART RXD in the released Kria PetaLinux BSPs. | |
| B31 | GND | Ground, connect to carrier card ground plane | |
| B32 | MIO38 | PS MIO signal on bank 501 | |
| B33 | MIO39 | PS MIO signal on bank 501 | |
| B34 | MIO40 | PS MIO signal on bank 501 | |
| B35 | GND | Ground, connect to carrier card ground plane | |
| B36 | MIO50 | PS MIO signal on bank 501 | |
| B37 | MIO51 | PS MIO signal on bank 501 | |
| B38 | Reserved | Not connected to SOM connector | |
| B39 | GND | Ground, connect to carrier card ground plane | |
| B40 | MIO58 | PS MIO signal on bank 502 | |
| B41 | MIO59 | PS MIO signal on bank 502 | |
| B42 | MIO60 | PS MIO signal on bank 502 | |
| B43 | GND | Ground, connect to carrier card ground plane | |
| B44 | MIO70 | PS MIO signal on bank 502 | |
| B45 | MIO71 | PS MIO signal on bank 502 | |
| B46 | MIO72 | PS MIO signal on bank 502 | |
| B47 | GND | Ground, connect to carrier card ground plane | |
| B48 | GND | Ground, connect to carrier card ground plane | |
| B49 | AC01UF | GTR_REFCLK1_C2M_P | PS-GTR REFCLK1 input, bank 505 |
| B50 | AC01UF | GTR_REFCLK1_C2M_N | PS-GTR REFCLK1 input, bank 505 |
| B51 | GND | Ground, connect to carrier card ground plane | |
| B52 | GND | Ground, connect to carrier card ground plane | |
| B53 | GTR_DP2_C2M_P | PS-GTR lane 2 RX, bank 505 | |
| B54 | GTR_DP2_C2M_N | PS-GTR lane 2 RX, bank 505 | |
| B55 | GND | Ground, connect to carrier card ground plane | |
| B56 | GND | Ground, connect to carrier card ground plane | |
| B57 | GTR_DP0_M2C_P | PS-GTR lane 0 TX, bank 505 | |
| B58 | GTR_DP0_M2C_N | PS-GTR lane 0 TX, bank 505 | |
| B59 | GND | Ground, connect to carrier card ground plane | |
| B60 | VCC_SOM | SOM main supply voltage, +5V | |
| Connector Row C | |||
| C1 | GND | Ground, connect to carrier card ground plane | |
| C2 | GND | Ground, connect to carrier card ground plane | |
| C3 | DBC | HPA00_CCP_CLK | HPIO clock-capable pin on bank 65 |
| C4 | DBC | HPA00_CCN | HPIO clock-capable pin on bank 65 |
| C5 | GND | Ground, connect to carrier card ground plane | |
| C6 | DBC | HPA03P | HPIO on bank 65 |
| C7 | DBC | HPA03N | HPIO on bank 65 |
| C8 | GND | Ground, connect to carrier card ground plane | |
| C9 | QBC | HPA08P | HPIO on bank 65 |
| C10 | QBC | HPA08N | HPIO on bank 65 |
| C11 | GND | Ground, connect to carrier card ground plane | |
| C12 | GC, QBC | HPA10_CCP_CLK | HPIO clock-capable pin on bank 65 |
| C13 | GC, QBC | HPA10_CCN | HPIO clock-capable pin on bank 65 |
| C14 | GND | Ground, connect to carrier card ground plane | |
| C15 | PU18_4p7 | PS_POR_B | PS power-on reset driven by the carrier card. When deasserted, the PS begins the boot process. |
| C16 | PU18_4p7 | PS_SRST_C2M_B | PS system reset driven by the carrier card. When asserted, forces the PS to enter the system reset sequence. |
| C17 | GND | Ground, connect to carrier card ground plane | |
| C18 | HDA06 | HDIO on bank 26 | |
| C19 | HDA07 | HDIO on bank 26 | |
| C20 | HDGC | HDA08_CC | HDIO clock-capable pin on bank 26 |
| C21 | GND | Ground | |
| C22 | HDA18 | HDIO on bank 26 | |
| C23 | HDA19 | HDIO on bank 26 | |
| C24 | HDA20 | HDIO on bank 26 | |
| C25 | GND | Ground, connect to carrier card ground plane | |
| C26 | PU18_2p2 | MIO24_I2C_SCK | PS I2C clock output, bank 500 |
| C27 | PU18_2p2 | MIO25_I2C_SDA | PS I2C serial data, bank 500 |
| C28 | PU18_10 | MIO12_FWUEN_C2M_B | PS MIO signal on bank 500. Optional default use as firmware update enable indication in the released Kria PetaLinux BSPs. |
| C29 | GND | Ground, connect to carrier card ground plane | |
| C30 | MIO29 | PS MIO signal on bank 501. Optional use as PMU input. | |
| C31 | MIO30 | PS MIO signal on bank 501. Optional use as PMU input. | |
| C32 | MIO31 | PS MIO signal on bank 501. Optional use as PMU input. | |
| C33 | GND | Ground, connect to carrier card ground plane | |
| C34 | MIO47 | PS MIO signal on bank 501 | |
| C35 | MIO48 | PS MIO signal on bank 501 | |
| C36 | MIO49 | PS MIO signal on bank 501 | |
| C37 | GND | Ground, connect to carrier card ground plane | |
| C38 | MIO55 | PS MIO signal on bank 502 | |
| C39 | MIO56 | PS MIO signal on bank 502 | |
| C40 | MIO57 | PS MIO signal on bank 502 | |
| C41 | GND | Ground, connect to carrier card ground plane | |
| C42 | MIO67 | PS MIO signal on bank 502 | |
| C43 | MIO68 | PS MIO signal on bank 502 | |
| C44 | MIO69 | PS MIO signal on bank 502 | |
| C45 | Reserved | No connect on the SOM | |
| C46 | GND | Ground, connect to carrier card ground plane | |
| C47 | AC01UF | GTR_REFCLK0_C2M_P | PS-GTR REFCLK0 input, bank 505 |
| C48 | AC01UF | GTR_REFCLK0_C2M_N | PS-GTR REFCLK0 input, bank 505 |
| C49 | GND | Ground, connect to carrier card ground plane | |
| C50 | GND | Ground, connect to carrier card ground plane | |
| C51 | GTR_DP3_M2C_P | PS-GTR lane 3 TX, bank 505 | |
| C52 | GTR_DP3_M2C_N | PS-GTR lane 3 TX, bank 505 | |
| C53 | GND | Ground, connect to carrier card ground plane | |
| C54 | GND | Ground, connect to carrier card ground plane | |
| C55 | GTR_DP1_C2M_P | PS-GTR lane 1 RX, bank 505 | |
| C56 | GTR_DP1_C2M_N | PS-GTR lane 1 RX, bank 505 | |
| C57 | GND | Ground, connect to carrier card ground plane | |
| C58 | GND | Ground, connect to carrier card ground plane | |
| C59 | VCC_SOM | SOM main supply voltage, +5V | |
| C60 | VCC_SOM | SOM main supply voltage, +5V | |
| Connector Row D | |||
| D1 | VCCO_HPA | HPA I/O voltage rail, 1.0V to 1.8V | |
| D2 | VCCO_HPA | HPA I/O voltage rail, 1.0V to 1.8V | |
| D3 | GND | Ground, connect to carrier card ground plane | |
| D4 | HPA02P | HPIO on bank 65 | |
| D5 | HPA02N | HPIO on bank 65 | |
| D6 | GND | Ground, connect to carrier card ground plane | |
| D7 | HPA01P | HPIO on bank 65 | |
| D8 | HPA01N | HPIO on bank 65 | |
| D9 | GND | Ground, connect to carrier card ground plane | |
| D10 | GC | HPA09P | HPIO on bank 65 |
| D11 | GC | HPA09N | HPIO on bank 65 |
| D12 | GND | Ground, connect to carrier card ground plane | |
| D13 | HPA14P | HPIO on bank 65 | |
| D14 | HPA14N | HPIO on bank 65 | |
| D15 | GND | Ground, connect to carrier card ground plane | |
| D16 | HDGC | HDA00_CC | HDIO clock-capable pin on bank 26 |
| D17 | HDGC | HDA01 | HDIO on bank 26 |
| D18 | HDA02 | HDIO on bank 26 | |
| D19 | GND | Ground, connect to carrier card ground plane | |
| D20 | HDGC | HDA12 | HDIO on bank 26 |
| D21 | HDGC | HDA13 | HDIO on bank 26 |
| D22 | HDA14 | HDIO on bank 26 | |
| D23 | GND | Ground, connect to carrier card ground plane | |
| D24 | PD50 | PWRGD_FPD_M2C | Power good indication for PS FPD power rails |
| D25 | PD50 | PWRGD_LPD_M2C | Power good indication for PS LPD power rails |
| D26 | PD50 | PWRGD_PL_M2C | Power good indication for all PL power rails |
| D27 | GND | Ground, connect to carrier card ground plane | |
| D28 | MIO26 | PS MIO signal on bank 501. Optional use as PMU input. | |
| D29 | MIO27 | PS MIO signal on bank 501. Optional use as PMU input. | |
| D30 | MIO28 | PS MIO signal on bank 501. Optional use as PMU input. | |
| D31 | GND | Ground, connect to carrier card ground plane | |
| D32 | MIO44 | PS MIO signal on bank 501 | |
| D33 | MIO45 | PS MIO signal on bank 501 | |
| D34 | MIO46 | PS MIO signal on bank 501 | |
| D35 | GND | Ground, connect to carrier card ground plane | |
| D36 | MIO52 | PS MIO signal on bank 502 | |
| D37 | MIO53 | PS MIO signal on bank 502 | |
| D38 | MIO54 | PS MIO signal on bank 502 | |
| D39 | GND | Ground, connect to carrier card ground plane | |
| D40 | MIO64 | PS MIO signal on bank 502 | |
| D41 | MIO65 | PS MIO signal on bank 502 | |
| D42 | MIO66 | PS MIO signal on bank 502 | |
| D43 | GND | Ground, connect to carrier card ground plane | |
| D44 | MIO76 | PS MIO signal on bank 502 | |
| D45 | MIO77 | PS MIO signal on bank 502 | |
| D46 | Reserved | No connect on the SOM | |
| D47 | GND | Ground, connect to carrier card ground plane | |
| D48 | GND | Ground, connect to carrier card ground plane | |
| D49 | GTR_DP3_C2M_P | PS-GTR lane 3 RX, bank 505 | |
| D50 | GTR_DP3_C2M_N | PS-GTR lane 3 RX, bank 505 | |
| D51 | GND | Ground, connect to carrier card ground plane | |
| D52 | GND | Ground, connect to carrier card ground plane | |
| D53 | AC01UF | GTR_REFCLK2_C2M_P | PS-GTR REFCLK2 input, bank 505 |
| D54 | AC01UF | GTR_REFCLK2_C2M_N | PS-GTR REFCLK2 input, bank 505 |
| D55 | GND | Ground, connect to carrier card ground plane | |
| D56 | GND | Ground, connect to carrier card ground plane | |
| D57 | GTR_DP2_M2C_P | PS-GTR lane 2 TX, bank 505 | |
| D58 | GTR_DP2_M2C_N | PS-GTR lane 2 TX, bank 505 | |
| D59 | GND | Ground, connect to carrier card ground plane | |
| D60 | VCC_SOM | SOM main supply voltage, +5V | |