Programmable Logic - DS985

Kria K24 SOM Data Sheet (DS985)

Document ID
DS985
Release Date
2025-05-22
Revision
1.2 English
The K24 SOM includes a custom-built Zynq UltraScale+ MPSoC (XCK24), that runs optimally (and exclusively) on the K24 SOM and includes a flexible and extensible programmable logic system (PL). The PL resources are summarized in the following table.
Table 1. PL Resources
Resource K24 SOM Description
System logic cells 154,350 Programmable logic cells for available
CLB flip-flops 141,120 Configurable logic block (CLB): Total number of flip-flops
CLB LUTs 70,560 Configurable logic block: Total number of look-up tables
Distributed RAM (Mb) 1.8 Distributed memory
Block RAM 216 Number of 36 Kb block RAMs
Block RAM (Mb) 7.6 Total block RAM memory footprint
UltraRAM blocks 0 288 Kb dual-port, 72-bit-wide memory with error correction
DSP slices 360 27 x 18 signed multiplier with 48-bit adder/accumulator
Video Codec 0 H.264 and H.265 supported simultaneous encode/decode
CMTs 3 Clock management tile
HDIO 23 High-density I/O supports 1.2V to 3.3V rails
HPIO 56 High-performance I/O differential pairs supports 1.0V to 1.8V rails
GTH transceivers 0 High-speed transceivers