Industrial Grade (K24I) Specifications - DS985

Kria K24 SOM Data Sheet (DS985)
Document ID
DS985
Release Date
2025-05-22
Revision
1.2 English

The industrial grade Kria K24I SOM (K24I) uses an exclusive Zynq UltraScale+ MPSoC with the speed/temperature grade of -2LI (VCCINT = 0.72V). This device is not specified in the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925). For some of the Zynq UltraScale+ MPSoC blocks, the -2LI (VCCINT = 0.72V) and -2LE (VCCINT = 0.72V) have the same switching characteristics. For the switching characteristics of -2LI that are the same as the -2LE, refer to the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925). For switching characteristics that are not the same as those in the data sheet and are relevant to the K24I SOM, refer to the following tables.

Table 1. Block RAM and FIFO Switching Characteristics
Symbol Description -2LI Speed Grade and Operating Voltage (VCCINT = 0.72V) Units
Maximum Frequency
FMAX_WF_NC Block RAM (WRITE_FIRST and NO_CHANGE modes) 516 MHz
FMAX_RF Block RAM (READ_FIRST mode) 495 MHz
FMAX_FIFO FIFO in all modes without ECC 516 MHz
FMAX_ECC Block RAM and FIFO in ECC configuration without PIPELINE 460 MHz
Block RAM and FIFO in ECC configuration with PIPELINE and Block RAM in WRITE_FIRST or NO_CHANGE mode 516 MHz
TPW 1 Minimum pulse width 578 ps
Block RAM and FIFO Clock-to-Out Delays
TRCKO_DO Clock CLK to DOUT output (without output register) 1.53 ns, Max
TRCKO_DO_REG Clock CLK to DOUT output (with output register) 0.44 ns, Max
  1. The MMCM and PLL DUTY_CYCLE attribute should be set to 50% to meet the pulse-width requirements at the higher frequencies.
Table 2. DSP48 Slice Switching Characteristics
Symbol Description -2LI Speed Grade and Operating Voltage (VCCINT = 0.72V) 1 Units
Maximum Frequency
FMAX With all registers used 600 MHz
FMAX_PATDET With pattern detector 524 MHz
FMAX_MULT_NOMREG Two register multiply without MREG 413 MHz
FMAX_MULT_NOMREG_PATDET Two register multiply without MREG with pattern detect 371 MHz
FMAX_PREADD_NOADREG Without ADREG 423 MHz
FMAX_NOPIPELINEREG Without pipeline registers (MREG, ADREG) 304 MHz
FMAX_NOPIPELINEREG_PATDET Without pipeline registers (MREG, ADREG) with pattern detect 280 MHz
  1. For devices operating at the lower power VCCINT = 0.72V voltages, DSP cascades that cross the clock region center might operate below the specified FMAX.