The K24 SOM provides a combination of fixed and user-defined functional interfaces. Each interface is implemented with one of the major systems within the MPSoC. The following table is a summary of the interfaces, and system association (PS or PL), with a description of their use.
| Interface | Physical Location | Linked Subsystem | Functional Description |
|---|---|---|---|
| QSPI |
MIO bank 500 MIO[5:0] |
PS | SOM QSPI memory |
| SD |
MIO bank 500 MIO[23:13] |
PS | SOM eMMC memory, MIO[22:13] = eMMC, MIO[23] = eMMC reset |
| I2C |
MIO bank 500 MIO[25:24] |
PS | SOM power management, EEPROM, and carrier card extensible I2C bus |
| SPI |
MIO bank 500 MIO[11:9], MIO[6] |
PS | Isolated SPI interface for TPM 2.0 security module |
| Power management |
MIO bank 501 MIO[34:32] |
PS | Fixed PMU SOM based power management |
| Power management |
MIO bank 501 MIO[31], MIO[35] |
PS | MIO35_PMU_GPO and MIO31_PMU_GPI: Optional PMU I/O signals for use by a carrier card designer |
| MIO – user defined I/O |
MIO bank 501 MIO[30:26], MIO[51:38] |
PS | 19 user-defined multiplexed CPU connected I/O pins |
| MIO – user defined I/O |
MIO Bank 502 MIO[77:52] |
PS | 26 user-defined multiplexed CPU connected I/O pins |
| LPDDR4 memory controller | MIO bank 504 | PS | SOM LPDDR4 memory |
| HDA | HDIO bank 26 | PL | 24 pins total, 23 available user-defined high-density input/output pins |
| HPA | HPIO bank 66 | PL | User-defined high-performance input/output pins, 18 differential pin pairs and one single-ended pin |
| HPA | HPIO bank 65 | PL | User-defined high-performance input/output pins, eight differential pin pairs, and three single-ended pins |
| PS-GTR transceivers | PS GTR 505 | PS | Four lanes of user-defined high-speed serial transceivers |
The K24 SOM provides a large number of flexible user-defined I/O that can be configured for various I/O standards and voltage levels. Voltage levels for each HDIO and HPIO bank can be customized by the SOM carrier card design to provide the application-required voltage rails to the corresponding I/O banks. See the Supported I/O Standards section for the I/O voltage rail pin definitions and corresponding decoupling requirements.
The K24 SOM provides PS-GTR transceivers to implement various high-speed protocols. The supported protocols are listed in the protocol tables of the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925), and are described in the Zynq UltraScale+ Device Technical Reference Manual (UG1085) and Zynq UltraScale+ MPSoC: Software Developers Guide (UG1137). The transceivers are configured via the AMD Vivado™ Design Suite.